Multiple access parallel memory and method

Details Multiple access parallel memory and method Multiple access parallel memory and method

1999-10-04

2004-04-27

Vanderpuye, Kenneth (Department: 2661)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S395710, C370S419000, C711S147000, C709S241000, C714S052000

Reexamination Certificate

active

06728254

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a memory architecture with multiple input ports. In particular it relates to a high throughput parallel memory shared across a number of input ports.
BACKGROUND OF THE INVENTION
A number of fields, including telecommunications, require a common memory structure for data received simultaneously through multiple input ports. ATM (Asynchronous Transfer Mode) is one example of a communications protocol for which a shared memory architecture is of particular benefit, as a result of the different data types supported by the protocol, and the requirement to multiplex together signals from different sources (for example audio and video).
A key component of ATM is the adaptation function. This provides the mechanism that adapts the carried service (e.g. voice, data) to and from the ATM domain. Several adaptation layers have so far been defined. ATM Adaptation Layer
1
(AAL
1
) is designed to adapt constant bit rate services (predominantly voice or video) into fixed length ATM cells. A key feature of AAL
1
is that it enables the timing relationship between the transmitter and receiver to be maintained over the asynchronous network. AAL
5
however has been predominantly designed to support data services. As such it provides a mechanism to segment long data packets into fixed length ATM cells and a mechanism to enable the integrity of the reassembled data packet to be validated after transmission across the network. AAL
5
is also being used in certain applications to carry voice services (particularly in computer desktop applications) where AAL
5
technology is readily available.
Both AAL
1
and AAL
5
adapt the carried service into a stream of fixed length ATM cell payloads. However for certain compressed voice services the length of the ATM cell payload (48 bytes) is too large; its use would lead to a large packetisation delay that in turn would affect existing network delay budgets and acceptable voice characteristics. To resolve this problem AAL
2
has been defined. AAL
2
supports a multiplex of user channels within a so-called single Virtual Channel Connection (VCC). Each user channel is carried in a stream of ‘mini-packets’—the length of the mini-packet payload for each channel can be defined according to the packetisation delay that can be tolerated. AAL
2
allows a single virtual channel (VC) to support multiple diverse services. In other words, a number of simultaneous voice, video and data channels can be multiplexed together to reduce packetisation delay. Furthermore, AAL
2
introduces a new switching layer above the ATM layer, for switching a mini-packet connection between channels.
There is a general need to provide a functional partitioning of an adaptation layer technology that enables these interworking requirements to be met with the flexibility to carry a call in any of the AALs. A key requirement of any adaptation layer partitioning is such that it optimises buffering apportionment in order to minimise the delay through any system and to minimise the memory and hence cost requirements of any implementation.
The need for a multiple access common memory structure is therefore apparent, to enable data from different sources to be processed and retransmitted at subsequent time intervals. To avoid data loss the memory must have the capacity to absorb data at the combined peak rates of all of the inputs.
One approach is simply to provide a unitary memory device capable of absorbing data at the combined peak rates of all of the input ports, with the most recent input written into the memory in the current cycle. However, the throughput capacity of currently available memory devices limit the number, or data rates, of the input ports in any practical application. Thus, the need for a development in the throughput of multiple access memory devices is highlighted. It is also possible to provide separate memory devices for each of the input ports. However, each memory device must then be capable of absorbing at the peak instantaneous data rate of its respective input port. This strategy is less optimum in terms of memory efficiency and complexity than providing a single common memory storage area. Furthermore, there is still a requirement to multiplex the data together after the separate memory buffers if the inputs carry data from multiple sources as in the AAL
2
structure.
Another possibility is to provide a memory capable of a throughput equal to the mean data rate of the input ports and to absorb data-rate fluctuations at each input port with suitable memory buffers. Each input port may be provided with a rate adaption FIFO capable of operating at the peak rate of the port. Each FIFO must be deep enough to absorb any fluctuations that may occur from the mean data rate. A multiplexer stage is required between the FIFOs and a common memory. This approach requires a careful balancing of FIFO depth and dilation rates against losses due to FIFO overflow. This strategy suffers a principal disadvantage in that the provisioning of the FIFOs requires detailed knowledge of typical peaks and troughs in the data rates through the input ports. Given that current communications networks experience highly random data rates, this strategy may result in equipment inefficiencies or data loss. A second disadvantage is that the FIFOs, in this strategy, cause an additional stage of data queuing resulting in data delays.
There is a need for a single stage, common memory that is capable of absorbing the combined maximum instantaneous data rates of a number of input ports while being capable of implementation using individual memory devices that need only operate at less than the maximum rate. This would allow the prevention of data loss irrespective of the traffic profiles at the input ports, providing the total payload memory is not exceeded.
In applications where asynchronous data streams, such as ATM AAL
2
, are employed it may be advantageous in some situations, such as multiple port interconnection, to have available a common memory capable of receiving data packets and partial data packets and storing them contiguously.
Applications where time-sensitive data is transmitted via an asynchronous system require data losses to be replaced, in sequence, with interpolated data. This may place higher instantaneous data-rate demands on the memory. It would also require some facility for writing interpolated data to the common memory in the correct relationship with correctly received data.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a memory architecture comprising a common memory structure having a plurality of data locations for storing data units and an input section for providing a plurality of input ports with access to the common memory structure, the input section including:
at least one memory buffer provided for each input port, each memory buffer capable of storing a number of data units at least equal to the number of input ports; and
at least one data bus allowing each of the memory buffers to write a plurality of data units substantially simultaneously to the memory structure at least once during a memory-access cycle,
the common memory structure including a plurality of memory banks equal to or greater than, in number, the number of input ports, each memory bank being accessible substantially simultaneously to receive data from a memory buffer.
The invention provides a set of memory buffers corresponding to a set of input ports, and a series of individual memory banks arranged in parallel and equal (or greater) in number to the number of input ports. A data word from each memory buffer may be written simultaneously across the series of memory banks, so that a high throughput memory is formed from a number of low throughput memory banks. The invention provides a common memory that is also capable of providing fair or prioritised access to memory locations for multiple input ports.
The input ports may be prioritised into at least one high priority input port(s) and at least one low priority input port(

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