Method of measuring dishing using relative height measurements

Details Method of measuring dishing using relative height measurements Method of measuring dishing using relative height measurements

2000-05-23

2004-03-02

Font, Frank G. (Department: 2877)

Optics: measuring and testing

Dimension

C356S630000, C356S237400, C356S237500, C356S600000

Reexamination Certificate

active

06700670

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to measuring properties in opaque features, and in particular to a metrology procedure to measure dishing that occurs in opaque features, e.g., after a chemical-mechanical polishing (CMP) step.
BACKGROUND
The metal interconnect of integrated circuits has conventionally been realized by blanket depositing a layer of metal on a planar insulating surface. Portions of the metal layer are subsequently removed in a photolithographically patterned etching step to form the resulting metal conductors. Conventional integrated circuits have generally employed somewhat resistive metal, such as aluminum, or metal alloys for the metal interconnect.
FIGS. 1A through 1G
show a cut-away view of the conventional fabrication of an aluminum interconnect. As shown in
FIG. 1A
, a relatively planar surface layer
10
, which may be, e.g., a silicon substrate, is covered with a dielectric layer
12
, e.g., an oxide layer, which is patterned and etched. An aluminum layer
14
, which may be an aluminum alloy, is blanket deposited over the dielectric layer
12
, as shown in
FIG. 1B. A
photoresist layer
16
is deposited over the aluminum layer
14
(FIG.
1
C), and is exposed and developed resulting in the structure shown in FIG.
1
D. The aluminum layer
14
is then etched, e.g., using a plasma etching technique, resulting in the structure shown in FIG.
1
E. The remaining photoresist layer
16
is removed resulting in the structure shown in FIG.
1
F. After these steps are completed, the surface is composed of metal lines with near vertical sidewalls above the surface of the dielectric layer
12
, as shown in FIG.
1
F. Subsequently, dielectric layers are deposited and etched over the metal lines to yield a dielectric layer
18
with a planarized surface, e.g., for the next metal layer, as shown in FIG.
1
G.
A major change is being implemented in semiconductor processing by switching from aluminum to copper metallization. Copper is preferred to aluminum due to its lower resistivity and better electromigration resistance. Unfortunately, copper is difficult to etch and the switch from aluminum to copper has forced a change in the basic metallization process. Copper cannot simply be substituted for aluminum in the metallization process because plasma etching of copper is more difficult than plasma etching of aluminum (due to the lack of volatile copper halogen compounds). Additionally, if copper is allowed to directly contact the dielectric materials, it can rapidly diffuse through dielectric materials and contaminate the semiconductor devices.
Thus, a “damascene” process has been developed whereby copper can be used as the interconnect metal. Rather than blanket depositing the interconnect metal on a substantially planar insulating substrate and then etching away parts of the metal layer to leave the conductors, trenches are formed in an insulating material. A composite layer of a diffusion barrier, nucleation layer and copper are then blanket deposited over the entire surface of the insulating substrate such that the trenches are filled. Chemical mechanical polishing is then used to planarize the integrated circuit surface and thereby polish away all the metal that is not in the trenches. The result is metal conductors disposed in trenches and a globally planarized surface.
FIGS. 2A through 2C
show a cut-away view of the conventional fabrication of a copper interconnect. As shown in
FIG. 2A
, a relatively planar surface layer
50
, which may be, e.g., a silicon substrate, is covered with a dielectric layer
52
, e.g., an oxide layer, which is patterned and etched. The dielectric layer
52
may be patterned and etched in multiple steps in order to produce trenches
54
and via
55
. A diffusion barrier layer (not shown), nucleation layer (not shown), and copper layer
56
are blanket deposited over the dielectric layer
52
such that the trenches
54
and via
56
are filled, as shown in
FIG. 2B. A
chemical mechanical polishing step is then used to planarize the surface of the copper layer
56
(along with the diffusion barrier layer and nucleation layer) with dielectric layer
52
, resulting in the structure shown in FIG.
2
C.
The ideal copper CMP process removes the copper, nucleation layer and diffusion barrier from the surface of the dielectric while leaving behind the copper, nucleation layer and diffusion barrier in the trenches and contacts or vias. The ideal result would be a globally planarized surface with no vertical height change over the entire wafer surface.
FIG. 3
shows the ideal resulting structure with a planar surface composed of a dielectric region
52
a
and idealized copper region
56
a
. Global planarity is desirable because of the depth of field requirements associated with the lithographic steps. Significant height variations on the surface will compromise the photoresist processing steps and subsequently the etching and metallization processes. Height variations also imply undesirable variations in the copper thickness and metal line resistance.
Unfortunately, because of the complexities associated with the CMP process, global planarity is not achievable. An artifact of the CMP processes in copper metallization results from the copper and dielectric material having different polishing rates, resulting in what is known as “dishing”.
FIG. 4
shows a cut-away side view of the typical resulting structure after the CMP process, in which the surface of the copper region
56
is lower than the surrounding dielectric region
52
. It should be understood that
FIG. 4
is for exemplary purposes and is not to scale. Dishing may generally be defined as the maximum height difference between the metal region
56
and the adjacent dielectric region
52
after CMP processing.
Another artifact caused by the CMP process, as known to those of ordinary skill in the art, is “dielectric erosion,” i.e., the dielectric regions exhibit a change in height over the surface of the wafer. This variation is related to the local density of metal features. Areas of low metal density exhibit the highest dielectric surface regions whereas areas of high metal density result in lower dielectric surface regions. Dielectric erosion, however, is beyond the scope of this disclosure.
The processing of silicon wafers to form integrated circuit chips requires many complex processing steps. Each step must be carefully monitored and controlled to maximize the quality and yield of the final product. With the imminent replacement of aluminum by copper to form the metallization layers on silicon wafers, new processes and metrology techniques must be developed and implemented.
Accordingly, what is needed is an economical, reliable, rapid, precise and accurate metrology procedure that will characterize and control the individual process steps in the copper metallization process and specifically that will address dishing that results from certain polishing methods, such as the CMP process.
SUMMARY
A metrology process, in accordance with the present invention, measures the dishing of a first feature, e.g., an opaque or metal line, that is surrounded by a second feature, e.g., a dielectric layer, on a production substrate by measuring the relative height of a plurality of first features having differing widths with respect to the second feature and adjusting the relative height to represent dishing based on at least one calibration point, which correlates a line width with a dishing value. The opaque feature may be, for example, a metal or metal alloy line containing, e.g., copper, aluminum, or tungsten, while the relatively transparent feature is a dielectric material. The metrology process is useful, for example, after the metal and dielectric materials undergo a polishing process, e.g., CMP, to approximately planarize the surface. The method includes generating a set of calibration data that correlates the magnitude of dishing with the width of a metal line. In addition, different sets of calibration data may be generated based on different parameters used in the

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