Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-09-16
2004-04-06
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S148000, C375S374000
Reexamination Certificate
active
06717446
ABSTRACT:
FIELD OF THE INVENTION
The present invention is generally related to a programmable charge-pump circuit. More particularly, the present invention is related to a charge-pump circuit with reduced charge injection characteristics from switching at the output of the charge-pump circuit, and reduced slewing in the charge-pump such that high speed operation is possible.
BACKGROUND OF THE INVENTION
Phase-locked loop (PLL) circuits are useful in many electronic systems. Applications for PLL circuits include master clock generation for a microprocessor system, clock generation for a sampling clock in an analog-to-digital converter system, clock generation for data recovery in a low-voltage differential (LVDS) driver/receiver system, clock generation for video systems, as well as others.
PLL applications typically provide an output clock signal by comparing the output clock signal to a reference clock signal. A phase-detector is often employed to compare the clock signals and provide a raw control signal to a loop filter. The loop filter is most commonly a low-pass filter (LPF) that is arranged to smoothed or averaged control signal in response to the raw unfiltered control signal. A voltage controlled oscillator (VCO) is often arranged to provide the output clock signal in response to the filtered control signal such that the output clock signal is locked in phase with the reference clock signal.
One example PLL circuit includes a phase detector that provides an UP and DOWN signal to a charge-pump circuit in response to the comparison between the output clock signal and the reference clock signal. The UP signal is active when the phase of the output clock is lagging behind the phase of the reference clock, while the DOWN signal is active when the phase of the output clock is leading the phase of the reference clock signal. The UP and DOWN signals are inactive when the phase of the output clock signal and the phase of the input clock signal are matched. The UP and DOWN signals activate a charging and discharging cycle in the charge-pump, where the output current from the charge-pump circuit is integrated on a capacitive type of load.
SUMMARY OF THE INVENTION
Briefly stated, a high-speed charge-pump circuit includes an array of current source/sinks circuits that are selectable according to UP and DOWN control signals, and a programmable setting. Each current source/sink circuit includes a current source circuit and a current sink circuit. The current source and current sink circuits are coupled to cascode circuits to minimize charge feed-through at the output of the charge-pump circuit. Matched switching circuits are configured to absorb charges that are injected at a common node between the cascode circuits and the current source/sink circuits. A clamp adjustment circuit is arranged to provide clamp voltages to the common node when the current source/sink circuits are in an off mode such that switching speeds are improved. The reduced switching-times permit the charge-pump circuit to operate at high speeds.
According to a feature of the invention, a programmable charge-pump circuit provides an output signal to an output node in response to UP and DOWN signals. The programmable charge-pump circuit includes a charge pump decoder circuit, an array of selectable current sources, and an array of selectable current sinks. The charge-pump decoder circuit is arranged to provide a first array of control signals in response to the UP signal and a program control signal. The charge-pump decoder circuit also provides a second array of control signals in response to the DOWN signal and the program control signal. The program signal determines which of the first and second array of control signals are selected in response to the UP and DOWN signals, respectively, such that the non-selected control signals from the first and second arrays are maintained at a constant logic level. Each of the selectable current sources includes a current source circuit that is selectively coupled to the output node through a corresponding cascode circuit when activated in response to a corresponding DOWN control signal from the first array of control signals. Each of the selectable current sinks includes a current sink circuit that is selectively coupled to the output node through another corresponding cascode circuit when activated in response to a corresponding UP control signal from the second array of control signals. By maintaining constant logic levels on the control signals for the non-selected current source and sink circuits, charge feed-through to the output node is minimized.
The present invention is also related to phase-locked-loop systems. An example phase-locked-loop system that is in accordance with the present invention may include a phase-detector circuit, a charge-pump circuit, a loop filter circuit, a current controlled oscillator circuit, and a counter circuit. The charge-pump circuit includes a charge-pump decoder circuit, an array of selectable current sources, and an array of selectable current sinks. The phase-detector circuit provides an UP signal and a DOWN signal by comparing an input signal phase to a clock signal phase. The charge-pump decoder circuit is arranged to provide a first array of control signals in response to the UP signal and a program control signal. The charge-pump decoder circuit also provides a second array of control signals in response to the DOWN signal and the program control signal. The program signal determines which of the first and second array of control signals are selected in response to the UP and DOWN signals, respectively, such that the non-selected control signals from the first and second arrays are maintained at a constant logic level. Each of the selectable current sources includes a current source circuit that is selectively coupled to the output node through a corresponding cascode circuit when activated in response to a corresponding DOWN control signal from the first array of control signals. Each of the selectable current sinks includes a current sink circuit that is selectively coupled to the output node through another corresponding cascode circuit when activated in response to a corresponding UP control signal from the second array of control signals. The loop filter circuit is coupled to the output node, wherein the loop filter is arranged to integrate current that is provided to the output node. The current-controlled oscillator circuit is coupled to an output of the loop filter circuit The counter circuit is coupled to an output of the current-controlled oscillator circuit, and configured to provide the clock signal. By maintaining constant logic levels on the control signals for the non-selected current source and sink circuits in the charge-pump circuit, charge feed-through to the output node is minimized.
According to another feature of the invention, a programmable charge-pump circuit provides an output signal to an output node in response to an UP signal, a DOWN signal, and a program signal. The programmable charge-pump circuit includes a means for decoding, first and second means for sourcing current, first and second means for enabling, first and second means for cascoding, and first and second means for disabling. The means for decoding is responsive to the program control signal, the UP signal, and the DOWN signal. The means for decoding is arranged to provide a first array of control signals in response to the UP signal and the program control signal, and also provide a second array of control signals in response to the DOWN signal and the program control signal. The program signal determines which of the first and second array of control signals are selected in response to the UP and DOWN signals, respectively, such that the non-selected control signals from the first and second arrays are maintained at constant logic levels. The first means for sourcing current is arranged to provide a first source current when active. The first means for enabling is arranged to selectively activate the first means for sourcing current in response
Hertzberg Brett A.
Merchant & Gould P.C.
National Semiconductor Corporation
Nguyen Minh
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