Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-06-06
2004-01-13
Le, Thong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S189011
Reexamination Certificate
active
06678191
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This disclosure relates to a nonvolatile semiconductor memory device having an electric erasable/programmable function, and more particularly, to a NAND Structure nonvolatile semiconductor memory device having electrically erasable and programmable memory cells.
2. Description of the Related Art
Generally, semiconductor memory devices are classified into two groups, that is, volatile semiconductor memory devices and a nonvolatile semiconductor memory devices. Volatile semiconductor memory devices can be further classified into a dynamic random access memory and a static random access memory. Volatile semiconductor memory devices have rapid speed in writing and reading, but have a disadvantage that contents stored in memory cells are erased when electric power supply is cut off.
Nonvolatile semiconductor memory devices are classified into mask read only memorys (MROM), programmable read only memorys (PROM), erasable and programmable read only memorys (EPROM), and electrically erasable programmable read only memorys (EEPROM). Since a nonvolatile semiconductor memory device permanently stores any contents in the memory cells even though an external electric power supply is cut off, the device is mainly used in storing contents that are required to remain therein irrespective of whether electric power is supplied or not.
However, a user cannot perform reading and writing (or programming) without restraint through an electronic system provided with the MROM, PROM, and EPROM. That is, it is not easy for a user to erase or reprogram contents programmed on-board. In contrast, since the EEPROM can perform electrically erasing and writing operations in its system itself, it has been applied and will continuously be applied as a system program storing device or a sub-memory device that need to have their contents continuously renewed.
In other words, various electronic systems being controlled by a recent computer or microprocessor have required an improved EEPROM having accurately erasable and programmable functions. Furthermore, since a battery powered computer system having a notebook size or portable computer size employs a hard disk device having a rotational magnetic disk occupying a relatively large area as a supplementary memory device, designers designing such systems have been very interested in developing a high integrated and high performance EEPROM, having a relatively small size.
It is very important to reduce the area occupied by memory cells in order to accomplish a high integrated EEPROM. In order to solve such a problem, an EEPROM having memory cells with a NAND structure, by which the number of select transistors per cell and the number of contact holes contacted with bit lines can be reduced, has been developed. As an example, such a NAND structure cell has been disclosed in pages 412 to 415 of IEDM under the title of “NEW DEVICE TECHNOLOGIES FOR 5V-ONLY 4 Mb EEPROM WITH NAND STRUCTURE CELL”, which is hereby incorporated herein.
Such a NAND structure cell will be explained below to provide better understanding for the present invention to be explained later.
The above-mentioned NAND structure cell consists of a first select transistor, a second select transistor, a source of which is coupled to a common source line, and eight memory transistors channels of which are in series connected between the source of the first select transistor and the drain of the second select transistor. The NAND structure cells are formed on a P type semiconductor substrate, and each of the memory transistors has a floating gate formed by forming a gate oxide film on a channel region between the source region and drain region and a control gate formed on the floating gate through an interlayer insulating layer. In order to program a memory transistor selected within the NAND cell unit, all of the memory transistors within the cell unit are erased, then programming operations are performed. The erasing operations of all of the memory transistors (generally called a flash erasing operation) are performed at the same time by applying 0 Volts to bit lines and, approximately 17 Volts to a gate of the first select transistor and control gates of all of the memory transistors. That is, all the memory transistors are converted to enhancement mode transistors, which are assumed to be transistors programmed by a binary digit “1”.
In order to program the selected memory transistors with a binary digit “1”, approximately 22 Volts is applied to bit lines, a gate of the first select transistor, and a control gate of each of the memory transistors between the first select transistor and the selected memory transistors. And, 0 volts is applied to a control gate of the selected memory transistor, a gate of the second select transistor and a control gate of each of the memory transistors between source lines and the selected memory transistors. Therefore, the selected memory transistor is programmed from a drain thereof to a floating gate by Fowler-Nordheim F-N tunneling of holes.
However, such a programming method has a problem in that a gate oxide film is stressed by a high voltage applied to a drain of the selected memory transistor and the stressed gate oxide layer accordingly causes current leakage there through. As a result, the ability of data retention in the memory cell is decreased as erasing and programming are continuously repeated, resulting in a decrease in the reliability of an EEPROM. In order to solve such a problem, an erasing and programming technique employing an improved device, in which NAND cell units are formed on a P type well region formed on an N type semiconductor substrate, has been disclosed on pages 129 to 130 of “symposium on VLSI Technology” published in 1990 under the title of “A NAND STRUCTURED CELL WITH A NEW PROGRAMMING TECHNOLOGY FOR HIGHLY RELIABLE 5V-ONLY FLASH EEPROM”. In the disclosures, the erasing operations of the memory cells, all the memory transistors within the NAND cell unit, are performed by applying 0 Volts to all the control gates and 20 Volts to the P type well region and the N type substrate. Electrons are evenly discharged from floating gates of all of the memory transistors to the P type wells. As a result, the threshold voltage of all of the memory transistors is converted to a negative voltage of −4V, and the transistors become in a state of depletion mode from which a binary logic “0” is assumed as being stored therein. In order to program the selected memory transistors within the NAND cell unit, a high voltage of 20 V is applied to a gate of the first select transistor and a control gate of the selected memory transistor, 0 V to a gate of the second select transistor, and a middle voltage of 7 V to a control gate of each of the non-selected memory transistors, respectively. If the selected memory transistor is programmed by a binary logic “1”, 0 V is applied to bit lines coupled to the NAND cell unit, thereby the floating gate of the selected memory transistor is implanted with electrons and the selected memory transistor is converted to a state of enhancement mode. In contrast, if the selected memory transistor is programmed by a binary logic “0”, a middle voltage of 7V to prevent programming is applied to the corresponding bit lines, thereby the programming operation of the selected memory transistor is prevented. Since such a programming operation allows electrons to be evenly implanted into the floating gate through the gate oxide layer from the P type well, partial stress is not created in the thin gate oxide layer, preventing current leakage in the gate oxide layer.
When system designers wish to perform an erasing operation to reprogram a part or block of programmed or written memory cells, a problem occurs. In this case, a generally used method is to simultaneously erase (eg. flash erasing) all of the memory transistors within memory cell array and thereafter reprogram all the contents already programmed and new contents to be programmed.
Therefore, since even the part or block of
Lee Seung-Jae
Lim Young-Ho
Le Thong
Marger & Johnson & McCollom, P.C.
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