Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-02-27
2004-05-11
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210, C365S185240, C365S185330, C365S189070, C365S201000
Reexamination Certificate
active
06735122
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and in particular, to the calibration of read and write operations of synchronous flash memory devices.
BACKGROUND OF THE INVENTION
Memory devices are typically utilized as internal storage areas in integrated circuit devices. There are several different types of memory. One type of memory is random access memory (RAM). RAM has traditionally been used as main memory in a computer environment. A related memory is synchronous DRAM (SDRAM), which uses a clock pulse to synchronize the transfer of data signals throughout the memory to increase the speed of the memory.
By contrast, read-only memory (ROM) devices permit only the reading of data. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
A synchronous flash memory has the ability to read several thousand cells at a time, as contrasted to 16 cells at a time in a typical standard flash device. High read speeds of less than 10 nanoseconds are possible with synchronous flash devices, making the devices comparable in speed to SDRAM. But unlike SDRAM, synchronous flash has a slow write speed, typically about 10 microseconds. The slow write speed of synchronous flash is due primarily to the high voltage transistors used in the write path. The high voltage transistors tend to be large, which adds capacitance to the path. This capacitance significantly slows the read process.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device to increase operating performance while maintaining proper operation.
SUMMARY OF THE INVENTION
The above-mentioned problems with non-volatile memory devices and other problems are addressed by embodiments of the present invention, and will be understood by reading and studying the following specification.
In one embodiment, a synchronous flash memory is disclosed. The synchronous flash memory includes a read sense amplifier, a verification sense amplifier, a switch, and an output buffer. The switch alternates electrical connection of the output buffer with the read sense amplifier and the verification sense amplifier. By measuring the distributions of voltage thresholds of erased cells versus voltage thresholds of programmed cells, differences in characteristics (offsets) between read state and write state of memory cells are determined. Thus, for a given sensing circuit, a specific margin is determined to ensure proper reads of the memory cells.
REFERENCES:
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patent: 6327181 (2001-12-01), Akaogi et al.
patent: 6377502 (2002-04-01), Honda et al.
patent: 6466480 (2002-10-01), Pekny
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
Yoha Connie C.
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