Discrete device socket and method of fabrication therefor

Details Discrete device socket and method of fabrication therefor Discrete device socket and method of fabrication therefor

2000-03-31

2004-01-06

Bradley, P. Austin (Department: 2833)

Electrical connectors

Metallic connector or contact having movable or resilient...

Spring actuated or resilient securing part

C439S072000, C439S525000

Reexamination Certificate

active

06672912

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to apparatus and fabrication methods for electrically connecting a discrete device to an integrated circuit, and more particularly to apparatus and fabrication methods for providing capacitance to an integrated circuit using discrete capacitors attached to a socket.
BACKGROUND OF THE INVENTION
Electronic circuits, and particularly computer and instrumentation circuits, have in recent years become increasingly powerful and fast. As circuit frequencies delve into the gigahertz region, with their associated high frequency transients, noise in the DC power and ground lines increasingly becomes a problem. This noise can arise due to inductive parasitics, for example, as is well known. To reduce such noise, capacitors known as decoupling capacitors are often used to provide a stable signal or stable supply of power to the circuitry.
Capacitors are further utilized to dampen power overshoot when an electronic device, such as a processor, is powered up, and to dampen power droop when the electronic device begins using power. For example, a processor that begins performing a calculation may rapidly need more current than can be supplied by available on-chip capacitance. In order to provide such capacitance and to dampen the power droop associated with the increased load, off-chip capacitance should be available to respond to the current need within a sufficient amount of time. If insufficient current is available to the processor, or if the response time of the capacitance is too slow, the die voltage may collapse.
Decoupling capacitors and capacitors for dampening power overshoot or droop are generally placed as close to the load as practical to increase the capacitors' effectiveness. Often, these capacitors are surface mounted to the electronic device or the package substrate on which the device is mounted. In some cases, the capacitors can be mounted to the die side of the package (i.e., the top side of the package where the die is mounted), the land side of the package (i.e., the bottom side of the package), or both.
FIG. 1
illustrates a cross-sectional view of an integrated circuit package
102
, upon which a die
104
, die side capacitors
106
, and land side capacitors
108
are mounted. Opposing leads of capacitors
106
,
108
are electrically connected, via conductive paths (not shown) in package
102
, to one or more die loads (not shown). These capacitors
106
,
108
provide capacitance for noise, power overshoot, and power droop dampening.
FIG. 2
illustrates an electrical circuit that simulates the electrical characteristics of the capacitors illustrated in FIG.
1
. The circuit shows a die load
202
, which may require capacitance or noise dampening in order to function properly. Some of the capacitance can be supplied by capacitance
204
located on the die. Other capacitance, however, must be provided off chip, as indicated by off-chip capacitor
206
. The off-chip capacitor
206
could be, for example, either or both the die side or land side capacitors
106
,
108
illustrated in FIG.
1
. The off-chip capacitor
206
may more accurately be modeled as a capacitor in series with some resistance and inductance. For ease of illustration, however, off-chip capacitance
206
is modeled as a simple capacitor.
The off-chip capacitor
206
must be located some distance from die load
202
due to manufacturing constraints. Accordingly, some inductance
208
exists between the die load and the off-chip capacitance. Because the inductance
208
tends to slow the response time of the off-chip capacitor
206
, it is desirable to minimize the distance between the off-chip capacitance
206
and the die load
202
, thus reducing the inductance value
208
. This can be achieved by placing the off-chip capacitor
206
as close as possible to the die load.
Land side capacitors
108
(
FIG. 1
) can be placed directly underneath a die on the bottom side of a package. Thus, in some cases (although not all), the electrical distance between land side capacitors
108
and a die load can be significantly shorter than can the path between die side capacitors
106
(
FIG. 1
) and a die load. This means that, often times, better performance can be achieved using land side capacitors
108
to provide the needed decoupling, rather than using die side capacitors
106
, which may be less effective.
Unfortunately, many applications, such as mobile applications, use packages where the input/output (I/O) leads to the die are centrally located and densely dispersed in an area directly underneath the die, referred to as the “I/O ring.” For example, land grid array and ball grid array packages include numerous I/O leads on the bottom side of the package within the I/O ring. In such applications, it is not practical to place the decoupling capacitors on the bottom side of the package under the die, because the capacitors would interfere with the physical and electrical connection of the package with the circuit board upon which it is to be mounted.
As electronic devices continue to advance, there is an increasing need for higher levels of capacitance at reduced inductance levels for decoupling, power dampening, and supplying charge. Accordingly, there is a need in the art for alternative capacitance solutions in the fabrication and operation of electronic and integrated circuit packages.


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patent: 5035629 (1991-07-01), Matsuoka
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patent: 5545045 (1996-08-01), Wakamatsu
patent: 5800184 (1998-09-01), Lopergolo et al.
patent: 6075285 (2000-06-01), Taylor et al.
Cotton, M., “Microfeatures & Embedded Coaxial Technology”,Electronic Circuits World Convention 8, 6 p., (Sep. 8, 1999).

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