Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-03-27
2004-07-20
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S503000, C257S522000, C257S751000
Reexamination Certificate
active
06765297
ABSTRACT:
CROSS REFERENCES TO RELATED APPLICATIONS
The present document is based on Japanese Priority Document JP 2001-090292, filed in the Japanese Patent Office on Mar. 27, 2001, the entire contents of which being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a wiring forming method in a semiconductor device and, more particularly to a semiconductor device in which a gap exists between wirings, and a wiring forming method in a semiconductor device.
2. Description of Related Art
In recent years, in a semiconductor device, multiple-layer wiring and miniaturization have been greatly advanced for the sake of higher performance. In a case of such a semiconductor device, as the miniaturization is advanced, parasitic capacitance between the wirings is increased, which leads to a serious problem for the development of a higher speed of a semiconductor device.
As a unit for reducing a drop in the parasitic capacitance, a technique of forming a gap between a plurality of wirings formed on a substrate is known (for convenience, it is referred to as a hollow wiring technique). The outline of an example of this hollow wiring technique will be described below with reference to sectional views of insulation layers of
FIGS. 9A
to
10
B and the like, on the basis of a technique disclosed in Japanese Patent Application Laid-Open JP-A-Heisei, 2-240947.
[Process
10
]
At first, a known transistor element (for example, MOS type FET) is formed on a semiconductor substrate. Then, a first insulation layer
110
is formed on the entire surface by using a CVD method. After that, for example, a lithography technique and a dry etching technique are used to form openings on the first insulation layer
110
. Then, for example, a sputtering technique and the dry etching technique are used to fill wiring material into the opening. Also, first wirings
111
are formed on the first insulation layer
110
. This situation is shown in
FIGS. 9A and 9B
. However, the illustrations of the semiconductor substrate, the transistor element and the openings are omitted in
FIGS. 9A
to
10
B. Also,
FIGS. 9A and 9C
and
FIG. 10A
are the views when the first insulation layer
110
and the like are cut on a plane vertical to a direction orthogonal to a direction in which the first wiring
111
is extended, and
FIGS. 9B and 9D
and
FIG. 10B
are the views when the first insulation layer
110
and the like are cut on a plane vertical to a direction parallel to the direction in which the first wiring
111
is extended.
[Process-
20
]
After that, after a second insulation layer
112
is formed on the entire surface by using the CVD method, planarization is performed on a surface of the second insulation layer
112
. Next, the lithography technique and the dry etching technique are used to form the openings on the second insulation layer
112
above the first wiring
111
. Next, for example, the sputtering technique and the dry etching technique are used to fill the wiring material into the openings. Also, second wirings
113
are formed on the second insulation layer
112
. This situation is shown in
FIGS. 9C and 9D
.
[Process-
30
]
Next, the second wiring
113
is used as an etching mask, and the second insulation layer
112
is etched. Accordingly, gaps
114
can be formed between the first wirings
111
and between the second wirings
113
. This situation is shown in
FIGS. 10A and 10B
. After that, thin insulation layer is formed on the entire surface, and the wiring structure is completed.
Also, a semiconductor device having a structure in which the gap between a plurality of wirings formed on the substrate is vacuum is also well known.
Such a hollow wiring technique is effective means for dropping the parasitic capacitance between the wirings. However, since the gap is filled with air or it is vacuum, this results in a problem that the thermal diffusion in the gap is poor. That is, the heat generation when the semiconductor device is operated causes the wiring to be deformed or cut away, and also brings about drop in reliability and occurrence of a trouble in the semiconductor device.
Therefore, the present invention provides a semiconductor device, in which the problem such as the defect of the thermal diffusion in the hollow wiring technique can be solved, and a wiring formation method in a semiconductor device.
SUMMARY OF THE INVENTION
A semiconductor device of the present invention to solve the above-mentioned problem is characterized in that a gap is formed between wirings on a substrate, and the gap is filled with gas having a thermal conductivity equal to or higher than three times that of air at 0° C.
By the way, in the following explanation, there may be a case where the gap, which is filled with the gas having the thermal conductivity (at 0° C.) equal to or higher than three times the thermal conductivity (2.4×10
−2
W (m
−1
) (K
−1
)) of the air at 0° C. is filled between the wirings, is referred to as the wiring structure in the present invention. Also, there may be a case where the gas having the thermal conductivity (at 0° C.) equal to or higher than three times that of the air at 0° C. is referred to as a highly thermally conductive gas, for the convenience.
In the semiconductor device of the present invention, preferably, one or more gas impermeable films through which the highly thermally conductive gas cannot be permeated are formed on the wiring and above the gap. Or, preferably, the lamination structure comprised of one or more gas permeable films, through which the highly thermally conductive gas can be permeated, and the gas impermeable films, through which the highly thermally conductive gas cannot be permeated, are formed on the wiring and above the gap. Here, silicon nitride (SiN) can be exemplified as the material constituting the gas impermeable film. By the way, preferably, the gas impermeable film made of the silicon nitride is formed by a plasma CVD method in the condition that the formed gas impermeable film has a compression stress. Also, the material constituting the gas permeable film can include the material constituting the gas permeable film in the explanation of a wiring forming method in a semiconductor device according to a first or third embodiment of the present invention, which will be described later.
A wiring forming method in a semiconductor device according to a first embodiment of the present invention includes the steps of:
(A) forming at least one wiring and a filling layer filled between the wirings, on a substrate;
(B) forming a gas permeable film on the wiring and the filling layer;
(C) removing the filling layer through the gas permeable film so as to form a gap between the wirings;
(D) filling a gas having a thermal conductivity equal to or higher than three times that of air at 0° C. through the gas permeable film into the gap; and
(E) forming a gas impermeable film on the gas permeable film.
In the wiring forming method in the semiconductor device according to the first embodiment of the present invention, the step (A) of forming the wiring and the filling layer filled between the wirings on the substrate can be comprised of, for example, the steps of forming the wiring on the substrate by using the known method; forming the filling layer on the entire surface by using a CVD method, a spin coating method, a sputtering method and the like; and then flattering the filling layer. Alternatively, it can be comprised of the steps of forming the filling layer on the substrate; forming a concave portion (for example, a groove) on the portion of the filling layer on which the wiring is formed; forming a wiring material layer on the entire surface including the concave portion by using an evaporating method, a sputtering method, a CVD method, a plating method and the like; selectively removing the wiring material layer on the filling layer by using a chemically mechanically polishing method (CMP method) and an etching-ba
Aoyama Junichi
Kobayashi Toshio
Lebentritt Michael S.
Menz Douglas M
Sonnenschein Nath & Rosenthal LLP
Sony Corporation
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