Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-12-08
2004-07-20
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S211000, C257S700000, C257S758000
Reexamination Certificate
active
06765298
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the design and fabrication of printed circuits and multi-layered substrates that are suitable for carrying signals with very high data rates. More particularly, the invention relates to techniques to reduce landing pad parasitic components and reduce the impedance discontinuity between the pad and the interconnect to the pad.
BACKGROUND OF THE INVENTION
Printed circuit boards (PCB) are used to couple signals among components that are mounted on the board. Components mounted on a board are typically electrically connected to the board through landing pads formed on the surface of the board, and are electrically coupled to other components through conductive interconnect elements.
As known in the art, multi-layered printed circuit boards are usually formed by the lamination of alternating layers of thin metal sheets and rigid dielectric materials. The metal layers are patterned to create conductive interconnecting elements in the form of microstrips running on the surface of the board, or striplines running in the interior layers of the board. Some of the metal layers are typically designed to serve as reference potentials, such as ground and components' supply voltages. These layers, which are often called reference potential planes, are typically interspersed between alternating signal layers. The dielectric provides structural integrity to the PCB and electrical isolation between the metal layers.
The data rates of the signals propagating through printed circuit boards are ever increasing. The increasing signal speed requires improvements in the signal fidelity as well as the interconnect's bandwidth when a signal propagates between two nodes in the printed circuit board. As known in the art, the interconnecting conductor, the adjacent reference potential planes, and dielectric layer are generally designed to form a transmission line having a pre-determined impedance, which is typically 50 ohms. In most applications, the widths of the landing pads are significantly larger than the widths of their associated interconnect conductors. Thus, the impedance of the landing pads is generally significantly lower than that of their associated interconnect conductors. This is due to the fact that the dielectric separation from the adjacent reference potential plane is the same for both the landing pads and the interconnect conductor, and impedance changes inversely to width. The lower impedance of the landing pads introduces excess parasitics that limit the bandwidth of the interconnecting conductor, and the impedance mismatch between the pad and the interconnecting conductor results in transmission problems in high-speed applications. One example is the use of a ball-grid-array (BGA) package in a multi-gigahertz printed circuit board. The landing pads of current state of the art BGAs are typically 25-30 mils in diameter, which is significantly larger than the typically 5 mil microstrips used in interconnecting conductors. Another example is a substrate used inside a BGA package. Typical solder ball landing pad sizes for current technology BGA substrates are on the order of 20-25 mil, significantly larger than the typically 3 mil traces used in microstrip interconnects.
The relatively large landing pad geometry creates an impedance mismatch, resulting in signal fidelity degradation caused by the superimposition of reflected energy from impedance discontinuity. The substantial impedance drop of the pad causes excess parasitic capacitance, which results in a reduction in bandwidth and slowing the signal transition rate.
One technique used to compensate the impedance mismatch is to reduce the width of a small section of the interconnecting conductor at the vicinity of the pad, with the goal being to keep an average impedance. However, signal reflections which could limit the performance of an interconnect are often caused by impedance discontinuities, especially for very high-speed signals.
Another technique believed to be used by some engineers in addressing the impedance mismatch problem is to remove some metal in the reference plane directly underneath the pad. However, the hole in the reference potential plane is typically larger than the pad, which potentially introduces an impedance discontinuity near the junction of the pad and the interconnect conductor.
In view of the foregoing, there are continuing efforts to decrease the parasitic capacitance of substrate landing pads and to provide better impedance matching between the traces and the landing pads.
SUMMARY OF THE INVENTION
In some embodiments, a printed circuit board is provided having a landing pad on the surface, coupled to a trace. A reference potential plane is disposed in the interior region running parallel to the surface. The plane is located above or below the trace, separated by a dielectric layer at a certain distance. The pad is configured to provide an impedance to the transmission line that is substantially matched to the impedance of the trace thereby substantially avoiding impedance discontinuity between the pad and the trace.
In some other embodiment, a printed circuit board is provided with a landing pad on the surface, coupled to an interconnecting trace. A reference potential plane is disposed in the interior region running parallel to the surface. The plane is located above or below the trace, separated by a dielectric layer at a known distance. The reference potential plane has an opening directly under or above the pad and is larger than the pad, thus raising the impedance of pad above that of the trace. The length of the pad is extended such that the junction between the pad and the trace is located directly above or below the boundary of the opening. At least one strip connected to a nearby reference potential, is patterned adjacent to the pad, and separated by a predetermined distance to the pad. The metal strips re-introduce enough parasitic capacitance to lower the pad's impedance to substantially match the impedance of the trace.
In other embodiments, a printed circuit board is provided with a landing pad on the surface, coupled to an interconnecting trace with pre-determined impedance. A plurality of reference potential planes are disposed in the interior region running parallel to the surface. The planes are located above or below the trace, separated by dielectric layers at known distances. The reference potential planes each has an opening directly under or above the pad and larger than the pad, raising the impedance of pad above that of the trace. The length of the pad is extended such that the junction between the pad and the trace is located directly above or below the boundary of the opening. At least one metal strip connected to a nearby reference potential is patterned adjacent to the pad, separated by a pre-determined distance to the pad. The metal strip(s) re-introduce enough parasitic capacitance to lower the pad's impedance to substantially match the impedance of the trace.
In yet other embodiments, a printed circuit board is provided with a landing pad on the surface, coupled to an interconnecting trace. A plurality of reference potential planes are disposed in the interior region running parallel to the surface. The planes are located above or below the trace, separated by dielectric layers at known distances. A consecutive number of the reference potential planes each having an opening directly under or above the pad and larger than the pad, raise the impedance of pad above that of the trace. The length of the pad is extended such that the junction between the pad and the trace is located directly above or below the boundary of the opening. At least one metal strip connected to a nearby reference potential, is patterned adjacent to the pad, and separated by a pre-determined distance to the pad. The metal strips re-introduce just enough parasitic capacitance to lower the pad's impedance to match the impedance of the trace.
These and other aspects, advantages, and objects of the present invention
Chin Tsun-kit
Landucci William
Beyer Weaver & Thomas LLP
National Semiconductor Corporation
Vu Hung
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