Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2002-06-17
2004-07-27
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S061000, C345S068000, C345S055000, C345S074100, C315S111210, C315S168000, C315S169200, C315S169300, C315S169400
Reexamination Certificate
active
06768479
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving method for driving a plasma display panel of a matrix display type.
2. Description of the Related Background Art
In recent years, in association with enlargement of a display apparatus, a thin-type display apparatus has been required and various thin-type display apparatuses have been put into practical use. As one of the thin-type display apparatuses, attention is paid to a display apparatus using an AC (alternating discharge) type PDP (plasma display panel).
FIG. 1
is a diagram schematically showing an arrangement of a plasma display apparatus including a plasma display panel and its driving device.
As shown in
FIG. 1
, a PDP
10
is provided with m column electrodes D
1
through D
m
serving as data electrodes, and n row electrodes X
1
through X
n
and n row electrodes Y
1
through Y
n
aligned to intersect with the respective column electrodes. Pairs of one row electrode X
i
(1≦i≦n) from the electrodes X
1
through X
n
and one row electrode Y
i
(1≦i≦n) from the row electrodes Y
1
through Y
n
are responsible for respective display lines of the PDP. The electrodes X
1
through X
n
and the row electrodes Y
1
through Y
n
form respective display lines of the PDP so that one row electrode X
i
(1≦i≦n) and one row electrode Y
i
(1≦i≦n) are in pairs for one display line. It is arranged in such a manner that the column electrode D and the row electrodes X and Y are placed to oppose each other with a discharge space filled with a discharge gas in between, and that a discharge cell corresponding to one pixel is formed at each intersection portion of the row electrode pairs and the column electrodes having the discharge space.
Herein, because each discharge cell emits light by exploiting a discharge phenomenon, it can take only two conditions: “a light emitting condition” and “a non-luminous condition.” In other words, each can display only two levels of luminance: the lowest luminance (non-luminous condition) and the highest luminance (light emitting condition).
A driving device
100
performs a gradation driving using the subfield method with respect to the PDP
10
arranged as above in order to achieve a half-tone luminance display corresponding to an input video signal. According to the subfield method, an input video signal is converted into, for example, 4-bit pixel data corresponding to each pixel, and as shown in
FIG. 2
, a display period of one field is divided into four subfields SF
1
through SF
4
to respectively correspond to the bit orders of the pixel data. As shown in
FIG. 2
, each subfield is given with the number of light emissions (or a light emitting period) corresponding to their respective weights.
FIG. 3
shows various kinds of driving pulses that the driving device
100
applies to the row electrode pairs and the column electrodes of the PDP
10
within each subfield shown in FIG.
2
and the application timings.
As shown in
FIG. 3
, the driving device
100
initially applies a reset pulse PR
x
of a positive polarity to the row electrodes X
1
through X
n
and a reset pulse RP
y
of a negative polarity to the row electrodes Y
1
through Y
n
. When these reset pulses PR
x
and RP
y
are applied, a reset discharge takes place in all the discharge cells of the PDP
10
, whereby wall charges of a predetermined quantity are formed uniformly in each discharge cell. Consequently, all the discharge cells of the PDP
10
are initialized to be in a “light emitting cell” condition (collective reset step Rc).
Then, the driving device
100
separates the bit orders in the 4-bit pixel data into the subfields SF
1
through SF
4
, respectively, and generates a pixel data pulse having a pulse voltage corresponding to the logical level of each bit. For example, in a pixel data writing step Wc in the subfield SF
1
, the driving device
100
generates a pixel data pulse having a pulse voltage corresponding to the logical level of the first bit of the pixel data. At this point, the driving device
100
generates a pixel data pulse having a pulse voltage at a high voltage when the logical level of the first bit is “1”, and generates a pixel data pulse having a pulse voltage at a low voltage (0 V) when the logical level of the first bit is “0”. Then, as shown in
FIG. 3
, the driving device
100
successively applies the pixel data pulses thus generated to the column electrodes D
1
through D
m
as one display line of pixel data pulse groups DP
1
through DP
n
for each of the first through n-th display lines. Further, the driving device
100
generates a scanning pulse SP of a negative polarity as shown in
FIG. 3
in sync with the application timing of each pixel data pulse group DP, and successively applies the same to the row electrodes Y
1
through Y
n
. At this point, a discharge (selective erasing discharge) takes place only in the discharge cells at the intersections of the display lines applied with the scanning pulse SP and the “columns” applied with the pixel data pulse of a high voltage, so that the wall charges formed within these discharge cells are lost. Consequently, the discharge cells initialized to be in the “light emitting cell” condition in the collective reset step Rc are changed to be in a “non-luminous cell” condition. On the other hand, the selective erasing discharge does not take place in the discharge cells applied with the scanning pulse SP and a pixel data pulse of a low voltage, and therefore, these discharge cells are sustained in the condition initialized in the collective reset step Rc, that is, the “light emitting cell” condition. In other words, each discharge cell of the PDP
10
is set to either the “light emitting cell” or “non-luminous cell” condition in response to the pixel data corresponding to the input video signal (pixel data writing step Wc).
Then, the driving device
100
repetitively applies sustain pulses IP
x
and IP
y
as shown in
FIG. 3
to the row electrodes X
1
through X
n
and the row electrodes Y
1
through Y
n
, respectively, in turn. The number of applications (or a period the application is continued) of the sustain pulses IP
x
and IP
y
applied during a light emission sustaining step Ic in each of the subfields SF
1
through SF
4
is, as set forth in
FIG. 2
, as follows given that “1” is the number of applications during the light emission sustaining step Ic in the subfield SF
1
:
SF1:
1
SF2:
2
SF3:
4
SF4:
8.
Herein, only the discharge cells holding residual wall charges within their discharge spaces, that is, the “light emitting cells”, discharge (sustained discharge) each time these sustain pulses IP
x
and IP
y
are applied. In other words, only the discharge cells in which the selective erasing discharge did not take place during the pixel data writing step Wc repeatedly emit light with the sustained discharge as many times as assigned to each subfield as described above, thereby sustaining the light emitting condition (light emission sustaining step Ic).
Finally, the driving device
100
applies an erasing pulse EP as shown in
FIG. 3
to the row electrodes Y
1
through Y
n
concurrently. When the erasing pulse EP is applied, an erasing discharge takes place in all the discharge cells of the PDP
10
, and the residual wall charges in the discharge cells are all lost (erasing step E).
A series of operations composed of the collective reset step Rc, the pixel data writing step Wc, the light emission sustaining step Ic, and the erasing step E are performed in each of the subfields SF
1
through SF
4
shown in FIG.
2
. According to this driving, light emissions with the sustained discharge are repeated a specified number of times corresponding to the luminance level of the input video signal throughout the display period of one field, and one can perceive the half-tone luminance corresponding to the number of light emission by sight. At this point, according to the gray scale driving based on the four subfields SF
1
through SF
4
as shown in
FIG. 2
, it is possible to display the
Kovalick Vincent E.
Pioneer Corporation
Shalwala Bipin
Sughrue & Mion, PLLC
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