Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
2002-01-07
2004-01-06
Nguyen, Truc (Department: 2833)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C439S066000, C439S083000, C439S382000, C439S487000, C439S067000
Reexamination Certificate
active
06672882
ABSTRACT:
This application incorporates by reference Taiwanese application Ser. No. 89125656, Filed Jan. 11, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a socket structure, and more particularly to a socket structure for Grid Array (GA) packages.
2. Description of the Related Art
In the development of IC packaging technology, the integrated circuit (IC) packages in Grid Array (GA) forms, such as Ball Grid Array (BGA), Flip Chip BGA and Land Grid Array (LGA) packages, have been evaluated as an important packaging type due to its great developing potential. The IC devices can be packaged by a variety of the exterior packaging materials, so that the IC device can be easily mounted on the printed circuit board (PCB) and the functions of IC signal transmission and heat dissipation are also achieved. In assembling the IC and PCB, the conventional method of pin through hole (PTH) is mostly replaced by the surface mount technology (SMT), in order to increase the assembly efficiency and density of the IC package. The PTH method means that the insertion of component leads into via holes for connecting and soldering the IC to the PCB. The SMT style means that the IC is soldered onto the PCB at high temperature without any insertion of component leads.
In order to increase the density of the IC package, the Area Array Package has gradually replaced the Peripheral Lead Package. This change indicates that the main goal is to develop low cost packages and higher package density and larger pin counts, so as to enhance the packaging yield. Accordingly, the Quad Flat Package (QFP) is replaced by the BGA and LGA, and the Tape Carrier Package (TCP) is replaced by the Flip Chip Package.
FIG. 1A
depicts the cross-sectional drawing of a conventional two-layer flip-chip LGA. The package
100
includes the IC
102
and the substrate
104
. The top surface of the IC
102
, which has the IC I/O pads, faces downward for the purpose of electrically connecting the IC I/O pads to the substrate
104
by the solder bump
106
. The periphery of the solder bumps
106
is further filled with the gel to form the underfill
107
for the purpose of mechanically protecting electrical connection between the IC I/O pads and the solder bump
106
. The substrate
104
further includes the first solder mask
108
, the second solder mask
110
and the vias
112
. The IC
102
is attached on the first solder mask
108
, while the Ni/Au plated contact land pads
114
form an array in the opening portion of the second solder mask
110
, as the name LGA (Land Grid Array) implies. A LGA package with (solder) bump pads (not shown) on the substrate
104
for the purpose of flip-chip die attachment is called a flip-chip LGA package. A flip-chip LGA substrate can have a two-layer (2 L) or multi-layer structure depending on the design requirement and available manufacturing capability. If the solder balls (not shown in
FIG. 1A
) are further attached on the Ni/Au plated contact land pads
114
in
FIG. 1
, the package
100
becomes BGA (Ball Grid Array) style. Simply stated, a flip-chip LGA package is essentially identical to a commonly seen flip-chip BGA package with the solder balls removed. Additionally, the vias
112
are between the first solder mask
108
and the second solder mask
110
to electrically connect the solder bumps
106
and the Ni/Au plated contact land pads
114
.
FIG. 1B
depicts the cross-sectional drawing of a conventional two-layer wire-bond LGA. The package
120
comprises the IC
122
and the substrate
124
. The bottom surface of the IC
122
, without IC I/O pads, adheres to the substrate
124
by the silver epoxy
126
. The substrate
124
further includes the first solder mask
128
, the second solder mask
130
, and the vias
132
. The IC
122
is attached on the first solder mask
128
, and the IC I/O pad of the IC die
122
is electrically connected to the substrate
124
by a wire bond method. For example, the opening area on the top side of the first solder mask
128
, which is electroplated with Ni/Au and called a bonding finger, is connected to the IC I/O pad by the gold wire
133
for transmitting the electrical signal of IC
122
to the substrate
124
. As the name wire-bond LGA (Land Grid Array) implies, the Ni/Au plated contact land pads
134
are attached to the opening portion of the bottom side of the second solder mask
130
and orderly form an array. If the solder balls (not shown in
FIG. 1B
) are further attached on the Ni/Au plated contact land pads
134
of the second solder mask
130
, the package
120
becomes wire-bond BGA (Ball Grid Array) package. Therefore, a wire-bond LGA package is essentially identical to a commonly seen wire-bond BGA package with the solder balls removed. Also, the vias
132
between the first solder mask
128
and the second solder mask
130
to connect the gold wire
133
and the Ni/Au plated contact land pads
134
, are the bridge of the electrical signal transmission. Additionally, the molding compound
136
is formed above the first solder mask
128
and encapsulates the IC die
122
for the purpose of protecting the wire bonded IC. The molding compound
136
prevents the wire bonded IC from corrosion and reduce the chance of IC destruction.
In order to mounting the package on the PCB, a socket is usually employed as an intermediate. The socket is usually mounted on the PCB by the PTH (pin through holes) method, and then the package is situated inside the socket. The drawback is that the socket rigidly soldered to the PCB by the leads is not easily removed or replaced when the socket is broken.
Some of the sockets are categorized as test sockets. A technique related to the test socket is disclosed in U.S. Pat. No. 5,290,193, “High density grid array test socket”, Goff, et al.
FIG. 2
depicts the cross-sectional drawing of the conventional test socket. The test socket
200
comprises the extension spring with the snap latches
202
a
and
202
b
, the pogo pins assemblies
204
a
and
204
b
. If the package
206
is pushed downward, the extension spring with the snap latches
202
a
and
202
b
are compressed and moved toward the left and the right side, respectively, to facilitate the electrical contact of the package
206
and the test socket
200
. After the package
206
is completely pressed down into the test socket
200
, the compressed snap latches
202
a
and
202
b
return to the original position and hold down the package
206
. The force balance of the snap latches
202
a
,
202
b
and the pogo pins assemblies
204
a
,
204
b
allows the package
206
to rest in the test socket
200
. However, the cost of this test socket is considerably high.
FIG. 3A
depicts the 3-dimentional drawing of another conventional socket for mounting on the PCB. Also, refer to FIG.
1
A. In
FIG. 3A
, the socket
320
mounted on the PCB
321
comprises the socket base
322
and the socket lid
324
. The socket base
322
has an open area
326
for aligning the package
100
. The hinge
328
, jointing the socket lid
324
and the socket base
322
, allows pivoting of the socket lid
324
on the socket base
322
. The socket lid
324
also has an open area
329
corresponding to the open area
326
of the socket base
322
. After the IC package
100
is seated within the open area
326
, the socket base
322
is covered with the socket lid
324
and fixed by the latching mechanism. For example, when the socket base
322
is covered with the socket lid
324
, the first fixing piece
330
a
and the second fixing piece
330
b
on the edge of the socket lid
324
are engaged with the first fixing clasp
332
a
and the second fixing clasp
332
b
. Additionally, the contacts (not shown in
FIG. 3A
) formed of a conductive material such as gold plated phosphor-bronze are arranged around the open area
326
and extend transversely through the socket base
322
. When the socket
320
is mounted on the PCB
321
, the contacts operate to electrically couple the socket base
322
and the IC package
100
to the underlying PCB
321
.
Nguyen Truc
Rabin & Berdo P.C.
Via Technologies Inc.
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