Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-07-12
2004-05-04
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S717000, C438S725000
Reexamination Certificate
active
06730608
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor processing, and more specifically to the processing of a field of a semiconductor wafer having alignment marks.
BACKGROUND OF THE INVENTION
Deposition and patterning are two of the basic steps performed in semiconductor processing. Patterning is also referred to as photolithography, masking, oxide or metal removal, and microlithography. Patterning enables the selective removal of material deposited on a semiconductor substrate, or wafer, as a result of deposition. For example, as shown in
FIG. 1A
, a layer
104
has been deposited on a substrate
102
. After the photolithography process is performed, as shown in
FIG. 1B
, some parts of the layer
104
have been selectively removed, such that gaps
106
a
and
106
b
are present within the layer
104
. A photomask, or pattern, is used (not shown in
FIG. 1B
) so that only the material from the gaps
106
a
and
106
b
are removed, and not the other portions of the layer
104
. The process of adding layers and removing selective parts of them, in conjunction with other processes, permits the fabrication of semiconductor devices.
Alignment is critical in photolithography and deposition, as well as in other semiconductor processes. If layers are not deposited properly, or if they are not selectively removed properly, the resulting semiconductor devices may not function, relegating them to scrap, which can be costly. Therefore, alignment marks are placed on the semiconductor wafer for the proper positioning during the deposition and photolithography processes. This is shown in
FIG. 2
, where the semiconductor wafer
202
has alignment marks, such as the alignment square
204
, thereon. When the photomask
206
is positioned over the wafer
202
, its own alignment marks, such as the alignment square
208
, is aligned with the alignment marks of the wafer
202
. For example, the alignment square
208
of the photomask
206
is aligned so that the alignment square
204
of the wafer
202
is centered therein.
For some types of semiconductor processing, alignment marks are placed in two fields, or areas, on opposite edges of the semiconductor wafer. This is shown in
FIG. 3. A
semiconductor wafer
300
is divided into a number of fields, such as the field
302
. Each field corresponds to one or more semiconductor devices, and represents an area of the semiconductor wafer that will be processed at a given time. For instance, a stepper may first process one field, then move on to the next field, and so on. The wafer
300
has an upper-right field
304
and a lower-left field
306
that have alignment marks
308
and
310
, respectively. The presence of the alignment marks
308
and
310
on the fields
304
and
306
presents difficulties with semiconductor processing of these fields, however. In particular, the alignment marks
308
and
310
should not be obscured, as may result from their processing, so that proper alignment for subsequent processing can still occur.
A conventional approach to ensure that the alignment marks
308
and
310
are not obscured is to only partially expose the fields
304
and
306
during photolithography, so that the alignment marks
308
and
310
are not exposed. This is shown in FIG.
4
. The part of the semiconductor wafer
300
is shown that includes the field
304
having the alignment mark
308
. The partial-image mask
402
prevents exposure of the part of the field
304
having the alignment mark
308
. The mask
402
is positioned over the field
304
, as indicated by the dotted line
404
, and the field
304
is exposed. The top part of the mask
402
prevents exposure of the top part of the field
304
that has the alignment mark
308
. The bottom part of the mask
402
includes a partial image for the field
304
, such that the bottom part of the field
304
is exposed. The mask
402
can be a positive photoresist mask. Partial exposure as shown in
FIG. 4
may be accomplished by, for example, blade adjustment of the semiconductor equipment being used.
The partial exposure process of
FIG. 4
has disadvantages, however. The resulting dimensions of the semiconductor device(s) of the field
304
defined by the partial exposure may be inaccurate as compared to the dimensions of the devices defined by the full exposure of other fields. These dimensions resulting from subsequent photolithography, etching, and chemical mechanical polishing (CMP). Furthermore, and possibly also causing the poor dimension uniformity, planarization of the unexposed part of the field
304
having the alignment mark
308
is not uniform to the exposed part of the field
304
and other fields adjacent to the field
304
. This is shown in FIG.
5
. The area
502
of the field
304
corresponds to the part of the field
304
that was exposed, whereas the area
504
of the field
304
corresponds to the part of the field
304
having the alignment mark
308
(not shown in
FIG. 5
) and which was not exposed, as divided by the dotted line
506
. The area
504
has a greater height than the area
502
does, resulting in a lack of planar uniformity.
Therefore, there is a need for exposing the fields of a semiconductor wafer on which there are alignment marks without employing a partial image exposure process. There is a need for such exposure without resulting in poor semiconductor device dimensions. Such exposure should also improve planarization of the parts of the fields having alignment marks, as compared to those parts that do not have alignment marks. For these and other reasons, there is a need for the present invention.
SUMMARY OF THE INVENTION
The invention relates to the full image exposure of a field of a semiconductor wafer on which there is an alignment mark. The field of the semiconductor wafer may be located at an edge of the wafer, such as the lower-left or upper-right edge of the wafer, and is exposed using a full-image mask, such as a positive photoresist mask, and that is preferably inclusive of the alignment mark. A clear out process is then performed around the alignment mark on the field of the semiconductor wafer to reveal the alignment mark. Prior deposition of photoresist or other layers, and subsequent exposure and stripping of the photoresist and etching of the other layers may also be performed.
The invention provides for advantages over the prior art. Because the entire field is exposed, and not just a part of the field as is done in the conventional partial image exposure process, the semiconductor devices fabricated using the invention have greater planar uniformity as compared to the conventional process. More specifically, there is greater planar uniformity between the part of the field in which the alignment mark is located and the rest of the field. This can result in improved dimensions of the resulting semiconductor devices as compared to those when using the conventional process. Still other advantages, embodiments, and aspects of the invention will become apparent by reading the detailed description that follows, and by referencing the attached drawings.
REFERENCES:
patent: 5705320 (1998-01-01), Hsu et al.
patent: 5897371 (1999-04-01), Yeh et al.
patent: 6184104 (2001-02-01), Tan et al.
patent: 6197481 (2001-03-01), Chang et al.
patent: 6529274 (2003-03-01), Hickman
Wolf et al., Silicon Processing for the VLSI Era, 1986, vol. 1, p. 407, 429.
Deo Duy-Vu
Kunemund Robert
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
LandOfFree
Full image exposure of field with alignment marks does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Full image exposure of field with alignment marks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Full image exposure of field with alignment marks will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3187250