Data processing: generic control systems or specific application – Specific application – apparatus or process – Article handling
Reexamination Certificate
2002-03-07
2004-09-07
Crawford, Gene O. (Department: 3651)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Article handling
C700S223000, C700S228000, C700S100000, C414S935000
Reexamination Certificate
active
06788996
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuit device manufacturing technology; and, more particularly, the invention relates to a technique that is effective when applied to production control in a production line for fabrication of a semiconductor integrated circuit device.
The production of a semiconductor integrated circuit device is generally controlled on the basis of an individual lot. One lot is normally formed by an aggregate of plural wafers, such as approximately 25 wafers. In a production line for a semiconductor integrated circuit device, in units of a lot, that is, in a state in which plural wafers forming one lot are housed in one carrier, conveyance between manufacturing devices is controlled, in addition to the production progress control of a product and processor allocation control. In production control technology examined by the present inventors, one lot (one carrier) is allocated to one manufacturing device as it is, and in the manufacturing device, the wafers in the lot are processed individually in sequence.
A technique related to a production line for a semiconductor integrated circuit device is disclosed in Japanese unexamined patent publication No.
2000-332080
, which describes a configuration wherein plural different processors are connected via a one sheet carriage mechanism, whereby semiconductor substrates can be carried to an individual processor one by one.
Also, Japanese unexamined patent publication No. Hei5(1993)-343497 discloses a wafer carriage technique wherein plural wafers to be inspected, that are housed in a predetermined cassette in the cassette stock, are extracted one by one and carried to plural wafer inspection stations for wafer inspection. Then, the wafers in the wafer inspection stations, for which inspection is completed, are carried to an original cassette and are housed therein.
Also, Japanese unexamined patent publication No. Hei3(1991)-289152 discloses a series of inspection process steps involving a technique in which, after wafers housed in a cassette are extracted one by one by carriage means, the carriage means is driven along a carriage route under computer control, is automatically guided to each of plural measurement units arranged on both sides of the carriage route and each wafer is inspected therein.
Also, Japanese unexamined patent publication No. Hei5(1993)-136219 discloses a technique for providing a carriage mechanism for carrying a semiconductor wafer and a carriage mechanism for carrying a probe card for checking the electric characteristics of the semiconductor wafers between a stocker and inspection equipment, so as to enable inspection according to the semiconductor wafer to be inspected. Also, Japanese unexamined patent publication No. Hei11(1999)-45916 discloses a technique in which plural probing stations are provided for testing a semiconductor wafer, and in which testing of semiconductor wafers one by one is effected in each probing station.
SUMMARY OF THE INVENTION
Recently, in the development of a production line for a semiconductor integrated circuit device, a reduction (quick turnaround time (QTAT)) of the manufacturing time of a semiconductor integrated circuit device has become an important aspect.
One QTAT technique for a semiconductor integrated circuit device, that was examined by the present inventors, involves a method of reducing the lot size (the number of wafers housed in a carrier). Thereby, the waiting time for processing of wafers in a lot can be reduced and the manufacturing time per process can be reduced. Also, since wafers are processed one by one in a one sheet processor in the manufacture of a semiconductor integrated circuit device, it can be expected that the manufacturing time can be further reduced by making the lot size equal one sheet. However, when the lot size was made equal to one sheet or was extremely reduced, it was first found by the present inventors that the following problems occurred. That is, multiple carriers were required in a production line, the load on the carriage between manufacturing devices (processes) was increased, and, conversely, the production efficiency tended to be deteriorated.
An object of the present invention is to provide a technique for reducing the manufacturing time in a production line for manufacture of a semiconductor integrated circuit device.
The foregoing and other objects of the present invention and new characteristics thereof will become more apparent from the description in the following specification and from the attached drawings.
Of the various aspects of the invention disclosed in this specification, a brief description of representative features will be summarized as follows.
That is, the invention is characterized by dividing plural wafers into groups of wafers in a control unit, allocating these groups of wafers to plural one sheet processors of the same kind and processing them in these one sheet processors in parallel.
Also, the invention proposes to divide plural wafers into groups of wafers in a control unit for every different manufacturing process according to a rule determined in each manufacturing process and to allocate the divided wafer groups to plural one sheet processors of the same kind in each manufacturing process and processing them in the plural one sheet processors in parallel.
Also, the invention includes a process for carrying plural wafers in a control unit to a manufacturing process, a process for dividing the plural wafers into wafer groups in the control unit according to a group of plural one sheet processors of the same kind used in the manufacturing process, and a process for allocating the divided wafer groups to the plural one sheet processors and processing them in the plural one sheet processors in parallel.
Also, in accordance with the invention, the divided wafer groups are allocated to the plural one sheet processors in a state in which each divided wafer group is housed in a respective carriage container.
Also, in accordance with the invention, the management of a vacant carriage container used after division and operation control are performed.
Also, in accordance with the invention, a vacant carriage container for housing a divided one or plural wafer groups is managed.
Also, in accordance with the invention, a vacant carriage container for housing a divided one or plural wafer groups is managed and the vacant carriage container is automatically carried to equipment for division.
REFERENCES:
patent: 5841677 (1998-11-01), Yang et al.
patent: 6092000 (2000-07-01), Kuo et al.
patent: 6201998 (2001-03-01), Lin et al.
patent: 6560507 (2003-05-01), Malitsky et al.
patent: 6584371 (2003-06-01), Sada et al.
patent: 6591163 (2003-07-01), Nakashima
patent: 03-289152 (1991-12-01), None
patent: 05-136219 (1993-06-01), None
patent: 05-343497 (1993-12-01), None
patent: 06-000753 (1994-01-01), None
patent: 09-153439 (1997-06-01), None
patent: 11-045916 (1999-02-01), None
patent: 2000-332080 (2000-11-01), None
Crawford Gene O.
Renesas Technology Corp.
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