Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-05-08
2004-09-28
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06798225
ABSTRACT:
FIELD OF THE INVENTION
The invention relates in general to systems for testing integrated circuits (ICs), and in particular to a system for distributing a single test signal output of an IC tester to multiple input terminals of one or more ICs and for determining states of output signals produced at multiple IC output terminals.
DESCRIPTION OF RELATED ART
As illustrated in
FIG. 1
, an integrated circuit (IC) manufacturer fabricates an array of ICs
12
on a semiconductor wafer
14
and then cuts the wafer to separate the ICs from one another. The manufacturer may then install the ICs in separate packages using bond wires to link the IC's input/output (I/O) terminals (conductive pads on the surface of each IC) to package pins providing signal paths to external circuits. Some ICs include “redistribution” layers covering its I/O terminals. Conductors within the redistribution layers link the IC's I/O terminals to contact pads formed on the top surface of the redistribution layers. The contact pads are larger than the IC's I/O terminals and are more evenly distributed so that the IC can be mounted directly on printed circuit boards (PCBs), for example by soldering the pads to correspondingly arranged contact pads on the surfaces of the PCBs. Spring contacts can also be used to link the IC's redistributed contact pads to a PCB's contact pads. The spring contacts may be formed either on the IC's contact pads or on the PCB's contact pads.
ICs may be tested at the wafer level before they are separated from one another or may be tested after they have separated. Referring to
FIG. 2
, an IC tester
10
for testing an array of ICs
12
residing on a wafer
14
(or for testing an array of singulated ICs held on a tray) typically includes a set of tester channels, each of which may either transmit a test signal to an IC input pad or monitor an IC output signal produced at an IC output pad to determine whether the IC responds correctly to its input signals. A set of coaxial cables
18
provides signal paths between the tester channels and a cable connector
16
on a probe board
20
. A set of probes
22
link pads on the lower surface of probe board
20
to the redistribution or I/O terminal pads on the upper surfaces of ICs
12
. Various types of structures can be used to implement probes
22
including, for example, wire bond and lithographic spring contacts, needle probes, and cobra probes. When spring contacts are used to implement probes
22
they may be formed either on pads on the upper surfaces of ICs
12
or on pads on the lower surface of probe board
20
.
U.S. Pat. No. 6,064,213, issued May 16, 2000 to Khandros et al., incorporated herein by reference, discloses an example of a card assembly designed to contact spring contacts formed on an IC. U.S. patent application Ser. No. 09/810,871 filed Mar. 16, 2001 (incorporated herein by reference) describes another example of a card assembly employing spring contact probes. U.S. Pat. No. 5,974,662 issued Nov. 2, 1999, issued to Eldridge et al., incorporated herein by reference, descries an example of a probe card assembly in which spring contacts formed on a probe card function as probes. The following documents (incorporated herein by reference) disclose various exemplary methods for manufacturing spring contacts: U.S. Pat. No. 6,333,269 issued Jan. 8, 2002 to Eldridge et al., U.S. Pat. No. 6,255,126 issued Jul. 31, 2001 to Mathieu et al., U.S. patent application Ser. No. 09/710,539 filed Nov. 9, 2000, and U.S. patent application Ser. No. 09/746,716 filed Dec. 22, 2000.
Probe board
20
is typically a multiple layer printed circuit board (PCB) providing signal paths between cable connector
16
and the pads on its lower surface. Traces formed on the various layers of probe board
20
convey signals horizontally while vias convey signals vertically though the layers.
Tester
10
typically provides a separate channel for each pad
26
that is linked to an I/O terminal of an IC to be tested.
FIG. 3
illustrates one channel
24
of a typical tester accessing a pad
26
of a wafer
14
via a path
36
through a probe card
20
. A test is usually organized into a succession of test cycles of uniform duration, and during each test cycle channel
24
may either provide an input to a pad
26
of an IC
12
formed on wafer
14
or may monitor an IC output signal produced by the IC at pad
26
to determine its state. A data acquisition and control circuit
30
, programmed via instructions supplied through a bus
42
, controls the action channel
24
is to carry out during each test cycle. When pad
26
is to receive an input signal, circuit
30
sets a tristate control input Z of a tristate driver
32
so that the driver supplies a test signal as input to pad
26
. Circuit
30
sets an input signal D to driver
32
during each test cycle so that the test signal is of the correct logic state. The test signal travels to pad
26
through a signal path formed by one of cables
18
, the signal path
36
provided by probe card
20
, and one of probes
22
.
When an IC
12
produces an output signal at pad
26
, the output signal passes through probe
22
, signal path
36
and cable
18
to become an input signal to a pair of comparators
38
and
39
within channel
24
. Comparator
38
asserts a compare high (CH) signal when the voltage of IC output signal is higher than a high logic level threshold voltage produced by a digital-to-analog converter (DAC)
40
. Comparator
39
asserts a compare low (CL) signal when the IC output signal voltage is lower than a low logic level threshold voltage produced by another digital-to-analog converter (DAC)
41
. Circuit
30
supplies control data DREF as input to DACs
40
and
41
for controlling the voltage levels of the VH and VL reference signals.
For example, when the test signal has 5 volt and 0 volt high and low logic levels, the VH and VL threshold levels might be set to 4.5 and 0.5 volts, respectively, so that an IC output signal over 4.5 volts is treated as a high logic level, an IC output signal under 0.5 volts is treated as a low logic level, and an IC output signal between 0.5 and 4.5 volts is considered neither high nor low logic level. Thus comparators
38
and
39
and DACs
40
and
41
can be thought of as an analog-to-digital converter (ADC) producing a 2-bit thermometer code output {CH, CL} indicating one of three ranges in which the input signal voltage lies.
Data acquisition circuit
30
samples the CH and CL bits at a time during each test cycle when the IC output signal is expected to be at a particular logic level. If the IC output signal is expected to be at its high logic level, then the CH bit should be true and the CL bit should be false when sampled. If the IC output signal is expected to be at is low logic level then CL should be true and CH should be false when sampled. An IC under test is considered to be defective when the sampled CH and CL bits representing the state of any of the IC's output signals are not of their expected states during any test cycle.
In some testers data acquisition and control circuit
30
stores the CH and CL bit for each test cycle in an acquisition memory so that a host computer can access the data via bus
42
at the end of the test and determine whether the IC is defective. In other testers circuit
30
may compare the sampled CH and CL data produced during each test cycle to their expected values and store cycle numbers in an internal memory referencing the particular test cycles, if any, for which the sampled data fails to match their expected values. The host computer then accesses the stored cycle numbers via bus
42
.
While tester channels
24
in some testers include two comparators as illustrated in
FIG. 3
, tester channels in other testers may include only a single comparator. For example when the low and high logic levels of an IC output signal are 0 and 5 volts, respectively, the comparator may be set to drive its single-bit output signal true when the IC output signal exceeds 2.5 volts.
Cuneo Kamand
FormFactor Inc.
Hollington Jermele
Smith-Hill and Bedell
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