Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2002-10-24
2003-11-11
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S750000, C257S762000
Reexamination Certificate
active
06646353
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor devices and their methods of fabrication. More particularly, the present invention relates to the processing of copper interconnect material and the resultant device utilizing the same. Even more particularly, the present invention relates to reducing electromigration in copper interconnect lines by doping their surfaces with barrier material using wet chemical methods.
BACKGROUND OF THE INVENTION
Currently, the semiconductor industry is demanding faster and denser devices (e.g., 0.05-&mgr;m to 0.25-&mgr;m) which implies an ongoing need for low resistance metallization. Such need has sparked research into resistance reduction through the use of barrier metals, stacks, and refractor metals. Despite aluminum's (Al) adequate resistance, other Al properties render it less desirable as a candidate for these higher density devices, especially with respect to its deposition into plug regions having a high aspect ratio cross-sectional area. Thus, research into the use of copper as an interconnect material has been revisited, copper being advantageous as a superior electrical conductor, providing better wettability, providing adequate electromigration resistance, and permitting lower depositional temperatures. The copper (Cu) interconnect material may be deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, electroless plating, and electrolytic plating.
However, some disadvantages of using Cu as an interconnect material include etching problems, corrosion, and diffusion into silicon.
1
These problems have sparked further research into the formulation of barrier materials for preventing electromigration in both Al and Cu interconnect lines. In response to electromigration concerns relating to the fabrication of semiconductor devices having aluminum-copper alloy interconnect lines, the industry has been investigating the use of various barrier materials. For instance, titanium-tungsten (Ti-W) and titanium nitride (TiN) layers have been used as well as refractory metals such as titanum (Ti), tungsten (W), tantalum (Ta), and molybdenum (Mo) and their silicates.
2
Although the foregoing materials are adequate for Al interconnects and Al—Cu alloy interconnects, they have not been entirely effective with respect to all-Cu interconnects. Further, although CVD has been conventionally used for depositing other metal(s) on an interconnect surface, CVD is not a cost-effective method of doping Cu interconnect surfaces with Ca ions. Therefore, a need exists for providing a method of fabricating a semiconductor device having Cu interconnect lines whose surfaces are doped with Ca ions for preventing electromigration and a device thereby formed.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of fabricating a semiconductor device having Cu interconnect lines, formed in vias of a semiconductor substrate, whose surfaces are selectively doped with calcium (Ca) ions for preventing electromigration and a device thereby formed. The present invention method reduces electromigration in Cu interconnect lines by restricting Cu diffusion pathways along the interconnect surface. This diffusion restriction is achieved by selectively doping the Cu interconnect surfaces with Ca ions from a chemical solution. More specifically, the present invention provides a method of fabricating a semiconductor device having a contaminant-reduced Cu—Ca/Cu interconnect line structure for reducing electromigration, improving interconnect reliability, and preventing corrosion, the method comprising: (a) providing a semiconductor substrate; (b) depositing a Cu interconnect line on the semiconductor substrate; (c) treating the Cu interconnect line in a chemical solution for facilitating selective doping of the Cu interconnect line with copper and calcium, thereby selectively forming a Cu—Ca—X film on the Cu interconnect line, wherein X denotes at least one contaminant; (d) processing the Cu—Ca—X film by sputtering under an argon (Ar) atmosphere, thereby effecting a thin Cu—Ca film on the Cu interconnect line; (e) annealing the thin Cu—Ca film, whereby the thin Cu—Ca film is alloyed, thereby forming a contaminant-reduced Cu—Ca alloy surface on the Cu interconnect line, and thereby forming a contaminant-reduced Cu—Ca/Cu interconnect line structure, comprising the contaminant-reduced Cu—Ca alloy surface, on the semiconductor substrate; and (f) completing formation of the semiconductor device. The annealing step primarily removes O and secondarily removes C and S, especially when performed in an environment such as a vacuum, an inert gas, or a reducing ambient such as an ammonia (NH
3
) plasma. Thus, the resultant device comprises a distinctive contaminant-reduced Cu surfaces selectively doped with calcium (Ca) on Cu interconnect lines formed in the vias of the substrate.
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Peter Van Zant, Microchip Fabrication: A Practical Guide to Semiconductor Processing, (1997), 392 and 397, 3rdEdition, McGraw-Hill USA.
Advanced Micro Devices , Inc.
Flynn Nathan J.
Greene Pershelle
LaRiviere Grubman & Payne, LLP
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