Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-07-25
2003-02-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S405000, C438S413000, C438S444000
Reexamination Certificate
active
06518147
ABSTRACT:
TECHNICAL FIELD
The present invention regards a process for manufacturing an SOI wafer by oxidation of buried channels.
BACKGROUND OF THE INVENTION
As is known, according to current processing techniques in the microelectronics industry, the substrate of integrated devices is obtained from monocrystalline silicon wafers. Recently, as an alternative to just silicon wafers, composite wafers have been proposed, so-called “SOI” (Silicon-on-Insulator) wafers comprising two silicon layers, one of which is thinner than the other, separated by a silicon oxide layer.
A process for manufacturing SOI wafers is the subject of European patent application No. 98830007.5, filed on Jan. 13, 1998 in the name of STMicroelectronics S.r.1., and is described hereinafter with reference to
FIGS. 1
to
8
.
According to this process, on a surface
3
of a substrate
2
, a first silicon oxide layer is initially grown having a thickness of between, for example, 20 and 60 nm. A first silicon nitride layer having a thickness of between 90 and 150 nm is then deposited. Using a resist mask, dry etching is carried out on the uncovered portions of the first oxide layer and the first nitride layer, and the resist mask is then removed, providing the intermediate structure of
FIG. 1
, where the wafer thus obtained is indicated, as a whole, by
1
, and the portions of the first oxide layer and of the first nitride layer that have remained after dry etching are indicated by
4
and
5
, and define respective first protective regions
7
covering first portions
8
′ of the substrate
2
.
The first protective regions
7
form a hard mask, indicated as a whole by
9
, which is used to etch the substrate
2
at second portions
8
″ left uncovered by the mask
9
, so as to form initial trenches
10
(FIG.
2
). Subsequently, as shown in
FIG. 3
, the wafer
1
is subjected to oxidation, to form a second oxide layer
11
which has a thickness of between, for example, 20 and 60 nm and covers the walls and the bottom of the initial trenches
10
, and then a second silicon nitride layer
12
is deposited for a thickness of between 90 and 150 nm.
Next, layers
12
and
11
are anisotropically etched without a mask. Given the anisotropy of the etching, the horizontal portions of the second silicon nitride layer
12
and second silicon oxide layer
11
on the bottom of the initial trenches
10
, and the portion of the second silicon nitride layer
12
above the portions
4
and
5
are removed, providing the intermediate structure of
FIG. 4
, wherein the regions
8
′ are still covered on top by the mask
9
and on the sides (i.e., on the vertical walls of the initial trenches
10
) by a silicon oxide portion
11
′ and by a silicon nitride portion
12
′. Instead, the substrate
2
is bare on the bottom
15
of the initial trenches
10
.
The uncovered silicon at the bottom
15
of the initial trenches
10
is then etched away, to deepen the initial trenches
10
themselves until final trenches
16
having a desired depth are obtained. In particular, the depth of the final trenches
16
determines the dimensions of the desired buried oxide layer, and hence the electrical characteristics of the SOI wafer, as will be described more clearly hereinafter, and consequently the depth is determined according to the specifications provided for the final SOI wafer.
The substrate
2
now comprises a base portion
2
′, and a plurality of “columns”
18
which extend vertically from the base portion
2
′. The intermediate structure of
FIG. 5
is thus obtained, wherein the silicon nitride portions
5
and
12
′ are no longer distinct from one another and are designated by
19
. The silicon oxide portions
4
and
11
′ are no longer distinct from one another and are designated by
20
and form, together with portions
19
, second protective regions
30
.
A thermal oxidation step is then carried out, so that the exposed silicon regions of the columns
18
are transformed into silicon oxide. In practice, oxide regions are gradually grown at the expense of the silicon regions, starting from the side walls of the final trenches
16
towards the inside of the columns and partly also towards and within the base portion
2
′. Since during oxidation there is an increase in volume, the oxide regions being formed gradually occupy the space of the final trenches
16
until they fill the trenches completely and join up together. The oxidation step terminates automatically once the columns
18
are completely oxidized (except for the top area or tip, designated by
21
, which is protected by the second protective regions
30
), thus forming a continuous buried oxide region
22
, shown in
FIG. 6
, where the vertical continuous lines indicate the meeting surfaces of the oxide regions being formed from the walls of two adjacent final trenches
16
, to highlight the expansion of the oxide.
Subsequently, by selective etching, the second protective regions
30
are eliminated so as to uncover the tips
21
, which form the germs for a subsequent epitaxial growth.
The structure of
FIG. 7
is obtained, showing the three-dimensional structure of the wafer
1
in this step. Next, an epitaxial growth is performed, the parameters of which are chosen to as to prevent nucleation of the silicon in the areas overlying the buried oxide region
22
, and a high ratio of lateral to vertical growth is chosen so as to obtain first a horizontal growth of the silicon around the tips
21
(and thus the coating of the top surface of the buried oxide region
22
), and subsequently the vertical growth of an epitaxial layer
23
. After an optional step of chemical-mechanical polishing to planarize the top surface of the wafer
1
, the final structure of the wafer
1
is then obtained, as shown in FIG.
8
.
Thereby, an SOI wafer can be produced using only process steps that are common in microelectronics, with much lower costs than those of processes currently used for forming SOI substrates.
The above described manufacturing process has, however, the drawback that the shape of the buried oxide region
22
is not ideal. In fact, as highlighted in the enlarged detail of
FIG. 9
, during thermal oxidation, the exposed silicon regions of the columns
18
are oxidized along curved lines, so that the buried oxide region
22
presents, underneath, a shape that is defined by a series of arches
35
and, on top, a shape defined by a series of cusps
37
extending upwards at each wall of the final trenches
16
. In addition, between the grown epitaxial silicon layer and the buried oxide layer, a void area
40
is present. This shape of the buried oxide region
22
renders critical the epitaxial growth of the silicon to form the SOI wafer, and, in addition, the void area
40
is a cause of non-optimal electrical characteristics.
SUMMARY OF THE INVENTION
The disclosed embodiments of the present invention overcome the drawbacks of the manufacturing process described above.
According to the disclosed embodiment of the present invention, a process for manufacturing SOI wafers and a SOI wafer are provided. The process includes forming cavities in a substrate of semiconductor material; growing an epitaxial layer of monocrystalline type on top of the substrate and the cavities to obtain a wafer of monocrystalline semiconductor material embedding the cavities, the cavities being completely surrounded by the monocrystalline material; and oxidizing the cavities to form at least one continuous region of buried oxide.
According to another aspect of the disclosed embodiments of the invention, a process for manufacturing an SOI wafer is disclosed that includes: forming first trenches in a substrate of semiconductor material; etching the first trenches to form cavities in the substrate of semiconductor material; growing an epitaxial layer of monocrystalline silicon on top of the substrate of semiconductor material to cover the trenches and the cavities formed therein; forming second trenches in the substrate of semiconductor material to extend a
Barlocchi Gabriele
Villa Flavio Francesco
Jorgenson Lisa K.
Niebling John F.
Pompey Ron
SEED IP Law Group PLLC
STMicroelectronics S.r.l.
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