Noise-immune pass gate latch

Details Noise-immune pass gate latch Noise-immune pass gate latch

1997-08-06

1999-08-17

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327203, H03K 3037, H03K 3289

Patent

active

059399155

ABSTRACT:
A non-buffered, noise-immune transmission gate latch for high performance applications is disclosed. The latch data input circuit contains an additional PFET for pulling up the gate of a transmission PFET and an additional NFET to pull down the gate of the transmission NFET to prevent the transmission gate from inadvertently opening when noise is coupled into the data input node. When data input voltage rises to Vdd+Vtp, the additional PFET begins to turn ON, and an inverted clock node is pulled above Vdd. The higher inverted clock node voltage is coupled to the gate of the transmission PFET and thereby prevents the transmission PFET from inadvertently turning ON. When data input voltage drops to -Vtn, the additional NFET begins to turn ON, and a clock node Is pulled below ground. The lower clock node voltage is coupled to the gate of the transmission NFET and thereby prevents the transmission NFET from inadvertently turning ON. Thus two additional transistors provide the necessary noise immunity.

REFERENCES:
patent: 4967108 (1990-10-01), Lee et al.
patent: 4974241 (1990-11-01), McClure et al.
patent: 5059836 (1991-10-01), Lee et al.
patent: 5081377 (1992-01-01), Freyman
patent: 5459421 (1995-10-01), Shaw
patent: 5465060 (1995-11-01), Pelella

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