Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

1996-08-13

2003-11-04

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S328000, C257S329000, C257S506000, C438S212000, C438S268000

Reexamination Certificate

active

06642599

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device including a lateral power device and a method of manufacturing the same.
2. Description of the Background Art
Power ICs (Integrated Circuits), which include a power element for a large current having a high breakdown voltage as well as its drive circuit and a protection circuit integrated integrally with the power element, will be the mainstream of power elements hereafter. It is preferable to perform gate driving in such a power element by a system of a voltage control type using an insulated gate electrode (MOS (Metal Oxide Semiconductor) gate). In this voltage control type, the gate driving requires less current compared with a current driving type.
Among integrated circuits (ICs) each including a plurality of semiconductor elements integrated on a single semiconductor substrate, ICs including a high breakdown voltage element are called power ICs. High breakdown voltage elements including an MOS gate such as a power MOSFET (Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor) are achieved utilizing combination of pn junction isolation and RESURF (Reduced Surface Field) technologies.
According to the pn junction isolation, an island of silicon surrounded by a p-type layer is formed, and the surrounded p-type layer is set to the lowest potential. Thereby, the inner n-type island and the outer p-type layer are always biased oppositely, so that a depletion layer of a high resistance exists at the pn junction.
The RESURF technology which was named by Apple Corp. and others is essentially the same as the offset gate technology which is used for accomplishing the lateral MOS transistor of high breakdown voltage.
A semiconductor device in the prior art will be described below in connection with a lateral p-ch (p-channel) MOS transistor having a structure similar to that disclosed in Terashima et al., Proc. ISPSD '93, pp. 224-229.
FIGS. 77 and 78
are a cross section and a plan schematically showing structure of a conventional semiconductor device. More specifically,
FIG. 77
is a cross section taken along line LXXVII-LXXVII in FIG.
78
.
Referring to
FIGS. 77 and 78
, an n
−
buried layer
903
is selectively formed at a p
−
high resistance substrate
901
. An n
+
buried layer
904
is formed on n
−
buried layer
903
.
An n
−
layer
905
is formed on p
−
high resistance substrate
901
. Around n
−
layer
905
, there is formed a p-type diffusion layer
963
having a substantially elliptical planar form for element isolation. The p-type diffusion layer
963
and p
−
high resistance substrate
901
form together with n
−
layer
905
a pn junction isolation. A lateral p-ch MOS transistor is formed at n
−
layer
905
thus isolated from other elements.
The lateral p-ch MOS transistor includes a p
+
source layer
909
, a p
+
drain layer
911
, a p
−
drain layer
915
, a gate oxide film
919
and a gate electrode layer
921
.
P
+
source layer
909
having a substantially elliptical planar form is formed at the surface of n
−
layer
905
and surrounds the periphery of n-type base layer
907
. At the surface of n
−
layer
905
is formed a p
+
drain layer
911
which has a substantially elliptical planar form and surrounds the periphery of p
+
source layer
909
with a predetermined space therebetween. P
−
drain layer
915
extends between p
+
drain layer
911
and p
+
source layer
909
and is located immediately under a field oxide film
969
. P
−
drain layer
915
surrounds the periphery of p
+
source layer
909
to define a channel region therebetween and is electrically connected to p
+
drain layer
911
to define, with p
+
source layer
909
, a channel region. A gate electrode layer
921
is formed on the surface of n
−
layer
905
, which is located between p
+
source layer
909
and p
−
drain layer
915
, with a gate oxide film
919
therebetween.
There is also formed an interlayer insulating layer
951
covering the p-ch MOS transistor. Interlayer insulating film
951
is provided with a through hole
951
b
exposing p
+
source layer
909
and n-type base layer
907
. Interlayer insulating film
951
is also provided with through holes
95
1
a
exposing portions of p
+
drain layer
911
.
There is formed an interconnection layer
953
b
for source leading, which electrically connects p
+
source layer
909
and n-type base layer
907
through through hole
951
b
. There is also formed an interconnection layer
953
a
for drain leading, which is electrically connected to p
+
drain layer
911
through through holes
951
a.
A plurality of conductive layers
927
formed on field oxide film
969
and a plurality of conductive layers
953
g
formed on interlayer insulating layer
951
form a multilayer field plate of a capacity coupling type. Conductive layer
927
among conductive layers
927
located at the outermost position is electrically connected to interconnection layer
953
a
through through holes
951
g.
Referring particularly to
FIG. 78
, interconnection layer
953
b
for source electrode leading, an interconnection layer (not shown) for gate electrode leading and interconnection layer
953
a
for drain electrode leading are formed on the same interlayer insulating layer
951
. Interconnection layer
953
a
for drain electrode leading has an elliptical planar form. Therefore, it is necessary to form a recess at conductive layer
953
a
and dispose interconnection layer
953
b
in the recess in order to keep isolation between interconnection layers
953
a
and
953
b.
A method of manufacturing the conventional semiconductor device will be describe below.
FIGS. 79
to
86
are schematic cross sections showing, in the order of steps, a method of manufacturing the conventional semiconductor device. Particularly,
FIGS. 79
to
86
show a portion corresponding to a region R
5
in FIG.
77
.
Referring first to
FIG. 79
, an n
−
buried layer
903
a
is selectively formed at p
−
high resistance substrate
901
, and an n
+
buried layer
904
a
is selectively formed at n
−
buried layer
903
a.
Referring to
FIG. 80
, n-type layer
905
is formed by epitaxial growth on p
−
high resistance substrate
901
. P-type diffusion layer
963
a
extending deep to p
−
high resistance substrate
901
is formed at a boundary between regions to be isolated. P-type diffusion layer
963
a
is formed in the substantially elliptical form extending around n
−
layer
905
.
Referring to
FIG. 81
, an oxide film
971
and a nitride film
973
are successively formed, and a resist pattern
975
is formed to cover regions not to be oxidized. Using resist pattern
975
as a mask, nitride film
973
is etched and removed. Thereafter, boron (B), i.e., p-type impurity is ion-implanted using resist pattern
975
as a mask. Thereafter, resist pattern
975
is removed. Thermal processing is performed by a conventional LOCOS (Local Oxidation of Silicon) method. Then, nitride film
973
is removed.
Referring to
FIG. 82
, the above thermal processing selectively forms field oxide film
969
at the surface of n
−
layer
905
. Also, p
−
drain layer
915
is formed immediately under field oxide film
969
.
Referring to
FIG. 83
, gate oxide films
919
a
and
925
a
are formed on exposed portions of the surface of n
−
layer
905
. Thereafter, polycrystalline silicon
921
a
doped with impurity (which will be referred to as a doped polycrystalline) is deposited on the whole surface. A resist pattern
973
a
having an intended configuration is formed on doped polycrystalline silicon
921
a
. Anisotropic etching is effected on doped polycrystalline silicon
921
a
using this resist pattern
973
a
as a mask. Thereafter, resist pattern

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