Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-04-16
2003-12-30
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S700000, C257S702000, C257S723000, C257S777000, C257S690000, C257S692000, C257S698000, C257S730000
Reexamination Certificate
active
06670700
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an interconnect substrate, a semiconductor device and a method of manufacturing the same, a circuit hoard, and an electronic instrument.
BACKGROUND OF ART
Multi-chip modules formed by mounting a plurality of semiconductor chips on an interposer have been known. An interconnect pattern is formed on the interposer. The interconnect pattern includes a plurality of lands for connecting a plurality of electrodes of the semiconductor chips and a plurality of lands for forming external terminals.
In the case where the lands for forming external terminals are concentrated in the region of the interposer on which one of the semiconductor chips is mounted, the interconnect pattern must be formed so as to run between the lands for connecting the electrodes of the semiconductor chip.
However, as electronic parts are mounted in higher density, there have been cases where no space is available for allowing the interconnect pattern to run between the lands. In such cases, the interconnect pattern must take a roundabout route in order to avoid the lands.
DISCLOSURE OF THE INVENTION
The present invention has been achieved to solve this problem. An objective of the present invention is to provide an interconnect substrate capable of preventing the interconnect length from increasing, a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic instrument.
(1) An interconnect substrate according to the present invention comprises:
an upper substrate including a mounting region for a first electronic chip and an upper interconnect pattern; and
a lower substrate including a first region to which the upper substrate is adhered, a second region including amounting region for a second electronic chip, and a lower interconnect pattern,
wherein the lower interconnect pattern comprises a plurality of first lower land sections which are formed in the center portion of the first region and are electrically connected to the upper interconnect pattern, a plurality of second lower land sections which are formed in the second region and electrically connected to the second electronic chip, and a plurality of lower connection sections which run outside the center portion in the first region and connect the first lower land sections to the second lower land sections.
According to the present invention, second upper land sections electrically connected to the first electronic chip and the second lower land sections electrically connected to the second electronic chip are formed on different substrates. Therefore, it is unnecessary to form the:lower connection sections between the second upper land sections. As a result, an increase in the interconnect length can be prevented.
Since the interconnect substrate according to the present invention uses the upper substrate and the lower substrate, the interconnect substrate can be formed at low cost in comparison with built-up substrates.
In addition, since the lower connection sections run outside the first lower land sections, the lower connection sections can be formed by effectively using space on the lower substrate.
(2) In this interconnect substrate, the upper interconnect pattern may comprise a plurality of first upper land sections which are formed in the center portion of the upper substrate and are electrically connected to the first lower land sections, a plurality of second upper land sections which are electrically connected to the first electronic chip, and a plurality of upper connection sections which connect the first upper land sections to the second upper land sections.
According to this feature, since the upper connection sections only connect the first upper land sections to the second upper land sections, the upper connection sections can be formed through the shortest route.
(3) In this interconnect substrate, the lower substrate may be rectangular, the first region and the second region may be disposed side by side, one end portion of a pair of parallel end portions of the first region and one end portion of a pair of parallel end portions of the second region may be disposed along one side of a pair of parallel sides of the lower substrate, and the other end portion of a pair of parallel end portions of the first region and the other end portion of a pair of parallel end portions of the second region may be disposed along the other side of a pair of parallel sides of the lower substrate.
(4) In this interconnect substrate, the second lower land sections may be formed in a pair of parallel end portions of the second region, and the second upper land sections may be formed in a pair of parallel end portions of the upper substrate above a pair of parallel end portions of the first region of the lower substrate.
According to this feature, the second lower land sections electrically connected to the second electronic chip are formed in the end portions of the second region of the lower substrate. The second upper land sections electrically connected to the first electronic chip are formed above the, end portions of the first region of the lower substrate. The second lower land sections and the second upper land sections are formed in rows.
A plurality of electrodes of the first and second electronic chips mounted on this interconnect substrate are formed in two parallel end portions. The first and second electronic chips are mounted with the electrodes being disposed on the end portions of the upper substrate and the lower substrate.
(5) In this interconnect substrate, the second upper land sections and the second lower land sections may be formed in the same arrangement pattern, and one of the second upper land sections and one of the second lower land sections formed at the same position in each arrangement pattern may be electrically connected to the same first upper land section and the same first lower land section.
According to this feature, the same, electronic chip as the first and second electronic chips can be used.
(6) In this interconnect substrate, dummy patterns electrically insulated from the upper interconnect pattern and the lower interconnect pattern may be formed in a pair of parallel end portions of the first region of the lower substrate to the same thickness as the lower interconnect pattern.
According to this feature, the upper substrate can be supported by the dummy patterns in the case where a lower interconnect pattern is not been formed under the second upper land sections of the upper substrate, whereby the pattern can be planarized.
(7) In this interconnect substrate, an insulation film may be formed on the lower connection sections at least in the area across the first and second regions.
This prevents occurrence of short circuits between the lower connection sections.
(8) In this interconnect substrate, the upper interconnect pattern may be formed on one surface of the upper substrate, the lower interconnect pattern may be formed on one surface of the lower substrate, and the surface of the upper substrate opposite to the surface on which the upper interconnect pattern is formed may be adhered to the surface of the lower substrate. on which the lower interconnect pattern is formed.
According to this feature, the upper interconnect pattern and the lower interconnect pattern respectively formed on the upper substrate and the lower substrate are disposed facing in the same direction.
(9) In this interconnect substrate, a plurality of through-holes may be formed in the upper substrate, and the first upper land sections and the first lower land sections may be electrically connected via the through-holes.
(10) In this interconnect substrate, the first upper land sections may be formed over the through-holes, the through-holes may be located over the first lower land sections, and a conductive material in contact with the first upper land sections and the first lower land sections may be provided in the through-holes.
(11) In this interconnect substrate, a plurality of through-holes for forming a plurality of external terminals which are
Oliff & Berridg,e PLC
Parekh Nitin
Seiko Epson Corporation
Thomas Tom
LandOfFree
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