Circuit for optimizing power consumption and performance

Details Circuit for optimizing power consumption and performance Circuit for optimizing power consumption and performance

2003-03-20

2003-12-02

Tran, M. (Department: 2818)

Static information storage and retrieval

Powering

Conservation of power

C365S189040

Reexamination Certificate

active

06657912

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to driver circuits, and more particularly to a circuit for optimizing power consumption and performance of driver circuits.
BACKGROUND OF THE INVENTION
Low power requirements in a circuit often conflict with high performance requirements. As a result, the voltage ranges at which circuits can operate can be limited in order to address this conflict. For example, circuit configurations that are efficient with regard to power, performance, and area are limited in that they can operate at one voltage but often cannot operate properly at other voltages, e.g., lower voltages. Conversely, circuit configurations that are designed for broad voltage operations often do not exhibit optimal power, performance, and area characteristics.
A classic example of the trade off between low power requirements and high performance requirements is that of a register file. A register file often includes an array of memory elements. All memory elements within a bit slice are connected to one another through a multiplexor. Each memory element within a bit slice could include, for example, one or more pass gates, each associated with a different word line. Incorporating the pass gates in each memory element and then coupling the pass gate outputs together within the bit slice effectively distribute the multiplexor.
FIG. 1
is a diagram of a first conventional multiplexed memory bit-line circuit. As is seen, a plurality of memory cells
201
are coupled to respective nfet devices
202
a
-
202
n
. The nfet device
206
which is controlled by a write through read (!WTR) signal, is active during a normal read operation and node-
2
will follow node-
1
, but it is delayed in time and will not achieve the same voltage uplevel. The inverter
212
whose output is connected to node-
3
, has a very high nfet to pfet ratio to cause a better response to the weak/poor rising response on node-
2
. As node-
3
falls, it activates the pfet feedback device
210
, which causes node-
2
to rise to Vdd eliminating any leakage current in inverter
212
associated with the weak “1” input.
As Vdd is reduced, the response of node-
2
is greatly degraded as the nfet device
206
connecting node-
1
and node-
2
, is on very weakly. In fact, as the Vdd is lowered further, node-
2
cannot achieve a voltage high enough to switch the inverter
212
. This is clearly a failure. One approach to resolving this failure is to apply the same boot-strap technique to the !WTR controlled device as is applied to the wordlines. This can and will work, but will raise the power associated with both the increased current demand on the voltage “doubler” and the power that will result on the bit lines being allowed to charge to a higher potential as the feedback device
210
raises node-
3
and ‘reverse’ loads the bit lines.
FIG. 2
illustrates a second conventional multiplexed memory bit-line. In this circuit
300
, the pass transistor connecting node-
1
and node-
2
is replaced by a transmission gate, T
1
, (nfet device
305
a
controlled by !WTR and pfet device
305
b
controlled by WTR) to improve performance and expand the Vdd operating range.
With the transmission gate configuration, node-
2
will now follow node-
1
, albeit rather slowly, and result in node-
2
having the identical voltages as node-
1
. The transient response of node-
2
will naturally be slow as the pfet device
305
b
portion of the transmission gate, while active, is on rather weakly. A major drawback of this configuration is the fact the once the inverter
312
, switches low, the output of the pfet feedback device
310
will now charge both node-
2
and node-
1
. Since node-
1
is the bitline that is highly capacitive, this will result in a slower falling response, but more importantly significantly higher power.
Accordingly, what is needed is a means to minimize power consumption while not compromising performance. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A memory bit line multiplexor circuit is disclosed. The circuit comprises at least one memory cell arrangement. The circuit includes a first active device coupled to the at least one memory cell arrangement and for coupling a first node to a second node within the circuit. The first active device is controlled by a write through read (!wtr) signal. The circuit includes a second active device coupled to the second node and a gate. The gate has a first input coupled to the first node; a second input coupled to the !WTR signal, and a third input being controlled by an inversion of the output of the circuit. The gate and the second active device provide a pulsed self-timed response that minimizes power consumption while optimizing performance of the circuit.
A circuit in accordance with the present invention is disclosed in which the most power, and area efficient realizations can be employed for applications requiring broad power supply operating ranges. The circuit employs a simple logic gate system configured to create a self-timed pulsed stimulus for allowing improved performance over a very broad Vdd operation range while simultaneously reducing power.


REFERENCES:
patent: 4779013 (1988-10-01), Tanaka
patent: 6087855 (2000-07-01), Frederick, Jr. et al.
patent: 6160749 (2000-12-01), Pinkham et al.
patent: 6208575 (2001-03-01), Proebsting
patent: 6269035 (2001-07-01), Cowles et al.
patent: 6462998 (2002-10-01), Proebsting

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