Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-03-21
2003-12-09
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S541000, C327S543000, C323S316000
Reexamination Certificate
active
06661279
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Application No. 2001-112463, filed on Apr. 11, 2001, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which an internal power supply voltage different from an external power supply voltage is used, and more particularly to a semiconductor integrated circuit within which a voltage lower than that of an external power supply is used.
2. Description of the Related Art
As for a related semiconductor integrated circuit, a technique of stepping down a voltage supplied from the outside to generate an internal voltage and using the internal voltage as an operating voltage of a MOS transistor is used for a semiconductor integrated circuit having a microstructural MOS transistor.
FIG. 5
shows the configuration of the periphery of a power supply voltage step down circuit of the related semiconductor integrated circuit.
An operating power supply voltage step down circuit
50
, a standby power supply voltage step down circuit
51
, a MOS circuit group
52
, a VREF generating circuit
53
, and a buffer
54
are provided here.
The power supply voltage step down circuits each receive an external power supply voltage VDDext supplied to a chip, generates an internal power supply voltage VDDint lower than the external power supply voltage VDDext, and supplies it to the MOS circuit group
52
via an internal power supply line IPL in the chip. The MOS circuit group
52
includes one or more MOS transistors, and, for example, it corresponds to a common CMOS circuit such as an inverter circuit or a NAND circuit, a memory cell, and the like.
The external power supply voltage VDDext differs depending on tip specifications of a semiconductor integrated circuit. For example, approximately 2.5 V or 1.8 V is used. In addition, the internal power sully voltage VDDint differs depending on the design rule or the like of a semiconductor integrated circuit. For example, approximately 1.2 V is used in a semiconductor integrated circuit having a 0.1 &mgr;m rule.
An operating state or a standby state of the chip is selected by a standby control signal STBY which is supplied from the outside of the chip to indicate the standby state. Namely, when the standby control signal STBY is at a low level, the operating state is selected, and when the standby control signal STBY is at a high level, the standby state is selected.
The operating/standby power supply voltage step down circuits
50
and
51
respectively have output P-type MOS transistors
55
and
56
, resistance elements
57
and
58
, and
59
and
60
for resistively dividing the internal power supply voltage VDDint, and the first operational amplifier
61
and the second operational amplifier
62
.
The first operational amplifier
61
and the second operational amplifier
62
respectively perform feedback control for the output P-type MOS transistors
55
and
56
in such a manner that the potentials of nodes FA and FB obtained by resistively dividing the internal power supply voltage VDDint are equalized to VREF, and hence the fixed internal power supply voltage VDDint is outputted irrespective of the level of the external power supply voltage VDDext.
In the operating/standby power supply voltage step down circuits
50
and
51
, the internal power supply voltage VDDint which is outputted to the internal power supply line IPL is set by using resistance division and the operational amplifiers
61
and
62
. In other words, in the operating/standby power supply voltage step down circuits
50
and
51
, the potential that the internal power supply voltage VDDint is resistively divided is applied to plus input terminals of the operational amplifiers
61
and
62
, and an output of the VREF generating circuit
53
is applied to minus input terminals of the operational amplifiers
61
and
62
.
The operating power supply voltage step down circuit
50
has large current driving force for the internal power supply voltage VDDint, but on the other hand, the current consumption of the voltage step down circuit itself is large. Since it is required to hold down the current consumption of the entire chip in the standby state, the operating power supply voltage step down circuit
50
is stopped by the standby control signal STBY, and only the standby power supply voltage step down circuit
51
is operated. In the standby voltage step down circuit
51
, the MOS circuit group
52
to which the internal power supply voltage VDDint is supplied is stopped in the standby state, whereby only small current driving force is required, resulting in a small current consumption of the voltage step down circuit itself. The operating/standby power supply voltage step down circuits
50
and
51
generate the internal power supply voltage VDDint having the same potential based on the reference voltage VREF. Namely, the internal power supply voltage VDDint outputted from the operating power supply voltage step down circuit
50
to the internal power supply voltage line IPL is the same as the internal power supply voltage VDDint outputted from the standby power supply voltage step down circuit
51
to the internal power supply voltage line IPL. It should be mentioned that both the operating power supply voltage step down circuit
50
and the standby power supply step down circuit
51
are operating in the operating state.
In the related semiconductor integrated circuit described above, there arises the following problem.
As the scale-down of a transistor used in a semiconductor integrated circuit advances and a gate insulating film of the MOS transistor becomes thinner, recently a gate leakage current of the MOS transistor has been given a great deal of attention as an obstacle to a reduction in the standby current of a chip.
For example, in a design rule of 0.15 &mgr;m, the thickness of the gate insulating film is approximately 3.5 &mgr;m. In a design rule of 0.1 &mgr;m, the thickness of the gate insulating film is approximately 2 &mgr;m. In the design rule of 0.15 &mgr;m, the gate leakage current does not matter, but in the design rule of 0.1 &mgr;m, a reduction in gate leakage current is needed.
Now, a voltage-current characteristic of the gate leakage current of the MOS transistor in the generation of the design rule of 0.1 &mgr;m is shown in FIG.
6
. As shown in
FIG. 7A
, a semiconductor substrate
65
, a source
66
, a drain
67
and a gate electrode
69
of a MOS transistor are connected in order to constitute a MOS capacitor, and then as shown in
FIG. 6
, a gate leakage current (a current flowing from the gate electrode
69
to the substrate
65
through a gate insulating film
68
) Ig per unit gate area is graphed by varying the gate voltage of the MOS capacitor. In
FIG. 7
, the same ground potential is applied to the semiconductor substrate
65
, the source
66
, and the drain
67
.
The gate electrode
69
is formed on the semiconductor substrate
65
with a gate insulating film
68
therebetween, and a gate voltage Vg is applied to the gate electrode
69
. The result of the measurements of the gate leakage current Ig flowing from the gate electrode
69
to the semiconductor substrate
65
in such a state is shown in FIG.
6
.
Since the MOS transistor in the generation of the design rule of 0.1 &mgr;m operates at a power supply voltage of 1.2 V, as can be seen from
FIG. 6
, the gate leakage current in this case is 1 nA per
1 &mgr;m
2
gate oxide film.
For example, the total gate area of a 36 Mbit low power consumption SRAM chip in this generation is 100 K&mgr;m
2
order, and hence the gate leakage current of the entire chip reaches 100 &mgr;A. Since the standby current specification of the low power consumption SRAM chip is usually not more than 100 &mgr;A, it becomes difficult to satisfy the standby current specification by only the gate leakage current in this generation. Moreover, due to ununiformity of p
Cunningham Terry D.
Kabushiki Kaisha Toshiba
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