Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
1999-12-10
2003-02-04
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S520000, C345S522000, C345S558000
Reexamination Certificate
active
06515670
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
This invention relates to a graphics system and to a method for minimizing the idle time of a host processor in the graphics system.
(b) Background of the Invention
Graphics accelerating devices (GAD) employed in graphics systems become more and more popular in personal computer applications, due to the rapid growth of the multimedia market and recent developments in VLSI technology. A conventional graphics system is illustrated in FIG.
1
.
The conventional graphics system comprises a host processor
10
, a system memory
20
, a graphics memory
30
and a GAD
40
′. The GAD
40
′ interconnects the host processor
10
and the graphics memory
30
via a system bus
50
and a memory bus
60
, and acts as a coprocessor to help the host processor
10
execute the graphics instructions. It is noted that the host processor
10
in a PC system is generally referred as the central processing unit (CPU). While the GAD
40
′ receives a graphics instruction sent from the host processor
10
, the GAD
40
′ fetches some specified graphics data, such as texture data, from the system memory
20
and executes the graphics instruction. After the performance of the graphics instructions, the graphics memory
30
receives and stores the outcome generated by the GAD
40
′.
The GAD
40
′ includes a buffer device (queue) and a graphics engine. The queue is used as a storage device for storing instructions received from the host processor
10
via the system bus
50
. The graphics engine is a graphics processor for receiving and executing the instructions stored in the queue. It accesses the graphics memory
30
via the memory bus
60
to store the outcome of graphics processing. Generally, the graphics memory
30
is a dynamic random access memory or a video random access memory.
However, due to the application of 3D graphics in a graphics system, a large amount of graphics data transferring occurs frequently between the host processor
10
and the GAD
40
′ in a graphics system. While a large amount of graphics data are transferred, the queue tends to be filled and the host processor
10
will be idle for awaiting available spaces of the queue. The host processor
10
is not idle only if the size of the queue is large enough. However, increasing the total capacity of the queue will necessitate the circuitry of the GAD
40
′ of the graphics system becoming complicated, thereby increasing the manufacturing cost.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a graphics system which sends graphics instructions to a graphics accelerating device by two ways to minimize the idle time of a host processor.
It is another object of the present invention to provide a method for minimizing the idle time of a host processor in the graphics system.
To achieve the above objects, in accordance with an preferred embodiment of the present invention, a graphics system is provided which comprises a host processor which generates graphics instructions and divides the graphics instructions into graphics commands and graphics data; a system memory which is used as a storage device; a graphics acceleration device which executes the graphics instructions received from the host processor; a graphics memory which is used as a storage device for storing graphics data processed by the graphics acceleration device; a system bus for transferring signals among the host processor, the system memory and the graphics acceleration device; and a memory bus for transferring signals among the graphics acceleration device and the graphics memory.
The graphics command is directly sent from the host processor to GAD via the system bus. On the other hand, the graphics data are stored in system memory temporarily. After the graphics command is received and executed by GAD, the related graphics data are sent from the system memory to the GAD via the system bus.
Therefore, the GAD handles the flows of graphics command and graphics data and performs the graphics instructions. The GAD comprises a graphics engine, a command master, and a data master. The graphics engine is a device which performs the operations of graphics instructions. In addition, it generates and handles the graphics data, which will be sent to the graphics memory via the memory bus. The command master provides buffer for the graphics commands received from the host processor. The data master receives request signals from the graphics engine, handshakes with a system bus controller, grabs the graphics data from the system memory and provides buffer for these data.
The method for reducing the idle time of a host processor in a graphics system according to present invention, comprising the steps of:
step 1: a host processor divides graphics instructions into graphics commands and graphics data;
step 2: the host processor sends the graphics command to a command master via a system bus;
step 3: the host processor sends the graphics data to a system memory;
step 4: a data master receives the graphics data from the system memory via the system bus;
step 5: a graphics engine receives the graphics command and the graphics data from the command master and the data master, respectively;
step 6: the graphics engine performs the graphics instructions and sends the processed outcome to a graphics memory for further display.
Other objects, features and advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5657479 (1997-08-01), Shaw et al.
patent: 5796413 (1998-08-01), Shipp et al.
patent: 5844576 (1998-12-01), Wilde et al.
patent: 5917505 (1999-06-01), Larson
patent: 5966142 (1999-10-01), Harkin
Huang Ta-Lun
Lu Chung-yen
Silicon Integrated Systems Corp.
Tung Kee M.
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