Semiconductor device manufacturing: process – Gettering of substrate – By vapor phase surface reaction
Reexamination Certificate
2002-05-06
2003-11-04
Thompson, Craig (Department: 2813)
Semiconductor device manufacturing: process
Gettering of substrate
By vapor phase surface reaction
Reexamination Certificate
active
06642128
ABSTRACT:
FIELD OF THE INVENTION
This invention generally involves a method for carrying out high temperature oxidations on semiconductor wafers including semiconductor features and more particularly to a method for carrying thin layer high temperature oxidations including forming shallow trench isolation (STI) oxide liners.
BACKGROUND OF THE INVENTION
In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Every device on the chip must be electrically isolated to ensure that it operates independently without interfering with another. The art of isolating semiconductor devices has become an important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper electrical isolation among devices will cause current leakage, and the current leakage can consume a significant amount of power as well as compromise functionality. Among some examples of reduced functionality include latch-up, noise margin degradation, voltage shift and cross-talk.
Shallow trench isolation (STI), is the preferred electrical isolation technique especially for a semiconductor chip with high integration. Broadly speaking, conventional methods of producing a shallow trench isolation feature include: forming a hard mask over the targeted trench layer, patterning a soft mask over the hard mask, etching the hard mask through the soft mask to form a patterned hard mask, and thereafter etching the targeted trench layer to form the shallow trench isolation feature. Subsequently, the soft mask is removed (e.g., stripped) and the shallow trench isolation feature is back-filled with a dielectric material.
In the STI technique, the shallow trench isolation area is first defined to form isolation trenches surrounding active areas of the wafer including a PAD oxide layer overlying the semiconductor surface, for example silicon, and a polish-stop nitride layer overlying the PAD oxide layer. The isolation trench is then thermally oxidized to grow a thin silicon dioxide liner according to a either a wet or dry oxidation process to cover the isolation trench surfaces followed by a high temperature annealing process to improve the quality of the oxide including increasing the density. The isolation trench is then filled with a chemical vapor deposited (CVD) oxide and chemically mechanically polished (CMP) back to the polish-stop nitride layer to form a planar surface. The polish-stop nitride layer is then removed, for example, according to a wet etching process.
Generally, silicon dioxide layers can be grown within a temperature range from about 400 C. to about 1150 C. in either wet or dry atmospheres respectively, followed by an annealing process at from about 1000° C. to about 1150° C. to improve the quality of the oxide. The growth and annealing process may be carried out in resistance-heated furnaces or in rapid thermal process chambers with heat provided by, for example, tungsten-halogen lamps. Typically, either a horizontal or a vertical furnace tube is used for this purpose. After loading a batch of wafers into a furnace, the furnace is heated to (ramped-up) a temperature suitable for oxidation of the silicon substrate. The wafers are then held at the elevated temperature for a period of time and then cooled (ramped-down) to a lower temperature.
During the oxidation process, as wafers are heated in the furnaces, a temperature profile within the furnace develops whereby the temperature at the wafer edge is higher than at the wafer center, leading to non-uniformity in oxide layer growth. The non-uniformity of the temperature profile and therefore the oxide layer uniformity increases as wafer size increases (e.g., from 200 mm to 300 mm). In a high temperature annealing process, oxygen is mixed with an inert carrier gas such as nitrogen, and is passed over a batch of process wafers at an elevated temperature of about 1000° C. to about 1150° C.
One problem according to the prior art high temperature annealing processes in forming thin oxide layers, for example, STI trench oxide liners, is that the oxide layer tends to peel at the periphery of the semiconductor wafer. In particular, semiconductor wafers located in particular areas of the annealing furnace in a batch anneal process tend to experience oxide layer peeling believed to be due to specific temperature profiles and gas flow behavior at those particular areas.
There is therefore a need in the semiconductor processing art to develop an improved high temperature oxide annealing process whereby peeling of thin oxide layers at a semiconductor wafer periphery is prevented.
It is therefore an object of the invention to provide an improved high temperature oxide annealing process whereby peeling of thin oxide layers at a semiconductor wafer periphery is prevented including overcoming other shortcomings and deficiencies of the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for preventing oxide layer peeling in a high temperature annealing process.
In a first embodiment, the method includes providing a plurality of spaced apart stacked semiconductor wafers for carrying out a high temperature annealing process including ambient nitrogen gas the plurality of spaced apart stacked semiconductor wafers stacked such that a process surface including an oxide layer of at least one semiconductor wafer is adjacent to a backside surface of another semiconductor wafer said backside surface having a layer of silicon nitride formed thereon prior to carrying out the high temperature annealing process; and, carrying out the high temperature annealing process.
REFERENCES:
patent: 5927992 (1999-07-01), Hodges et al.
patent: 6051346 (2000-04-01), Kornblit et al.
patent: 6235608 (2001-05-01), Lin et al.
Huang Kuo-Bin
Lu Ching-Shan
Twu Jih-Churng
Taiwan Semiconductor Manufacturing Co. Ltd
Thompson Craig
Tung & Associates
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