SRAM bit line architecture

Details SRAM bit line architecture SRAM bit line architecture

2002-12-04

2003-12-02

Elms, Richard (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S069000

Reexamination Certificate

active

06657880

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
Current static random access (SRAM) chip architecture uses a six-transistor (6T) memory cell. Connections for a bit line (BL) and a complementary bit line (BLN) to a 6T SRAM are run in either a metal
2
connection layer or a metal
3
connection layer, but not in both metal connection layers together. The 6T memory cells are arranged in columns, where each column has a common bit line and a common complementary bit lines.
2. Prior Art
If the directions in a DRAM chip are visualized as orthogonal three-dimensional x, y, and z directions, each metal connection layer can be thought of as generally being in a horizontal, or x, y plane. Each metal connection layer, such as a metal
2
layer or a metal
3
layer, is then thought of as being located in a separate horizontal plane, where the horizontal planes are vertically spaced over each other in the z direction. A vertical plane is one that runs perpendicular to a horizontal plane. The bits lines and the complementary bit lines for a column of 6T memory cells are visualized as generally running in the y direction in a horizontal plane of with a row of memory, cells running in the x direction. A straight bit line and a straight complementary bit line run parallel in the same metal layer, or horizontal plane.
In a conventional SRAM, the bit lines and the complementary bit lines for a column of memory cells are in the same horizontal metal layer and, consequently, run parallel and alongside of each other and alongside of the neighboring bit lines and complementary bit lines of their neighboring columns of memory cells.
As a consequence of this arrangement, these bit lines and complementary bit lines crosstalk to each other via the coupling capacitance between these like metal lines. Both a bit line and its corresponding complementary bit line are precharged to a ONE, or HIGH, level. A bit line or complementary bit line that is being pulled down from a precharged level is capacitively coupled to a neighboring complementary bit line or bit line and pulls it down from the precharged level. The result of this is to reduce the difference in voltage between the bit line and the complementary bit line of a particular column that is being presented to the differential input terminals of a differential sense amplifier. This reduced input voltage difference reduces the input voltage margin of the senseamp and requires a longer BL/BLN voltage differential buildup time to offset the effect of this ‘talking’ or parasitical capacitive coupling. This slows down the sensing process and results in more time being required to accurately read the contents of a memory cell.
FIG. 1
illustrates one previous method designed to partially alleviate capacitive coupling between lines. This method horizontally twists, or displaces, the BL and BLN lines with respect to the BL and BLN lines of a neighboring column.
Bit lines are designated as B
0
, B
1
, B
2
, etc., and complementary bit lines are designated as B
0
N, B
1
N, B
2
N, etc. Line pairs for B
0
/B
0
, B
2
/B
2
, B
4
/B
4
each have a single standard twist, that is, one horizontal twist in their length. Alternate line pairs B
1
/B
1
, B
3
/B
3
, B
5
/B
5
each have a triple standard twist, that is, two horizontal twists in their length.
This twisting is accomplished in the twist regions by utilizing a metal layer that is either higher or lower than the original metal level to provide appropriate connections for a horizontal twist. After the twist, both BL and BLN still run in the same metal layer. For example, if the metal lines are in metal layer
2
, metal layers
1
or
3
are used to provide crossover connections for the metal lines that still remain in metal layer
2
. This horizontal twist method can reduce coupling between the lines of neighboring columns, but does not affect the coupling between a particular column's own BL and BLN lines because the BL line and the BLN line are still adjacent to each other in the same metal plane.
As a result of advancements in semiconductor processing techniques, less space is available between metal lines so that the metal lines are required to be more closely spaced next to each other. In order to keep the ohmic resistance of these narrower, more closely spaced lines low, it is necessary to make these metal lines thicker in the vertical, or z, direction. This increased thickness increases the side areas of the lines and reduces the distance between these larger side areas. This produces greater coupling capacitance between these thicker, more closely spaced metal lines and results in a serious major first order effect on performance due to increased talking between these thicker lines.
Consequently, what is needed is an improved technique for routing these thicker, more closely spaced metal lines.
Certain DRAM bit line architectures, such as described in U.S. Pat. No. 6,222,275, use what is called “vertical twisting.” As shown in
FIG. 2
, BL and BLN are directly in line horizontally, so that BL and BLN will still talk to each other via the capacitance between the conductors. The reasons given in the patent for a vertically stacked bit-line architecture for DRAM patents is to provide relief of the lower packing density of the folded bit-line architecture which also cannot utilize a cross-point layout cell structure resulting in an inefficient use of the cell matrix space. The term ‘vertical twisting’ as used in this patent refers to a different layout that was done for different reasons than reducing the BL and BLN crosstalk. In fact, the DRAM layout of BL and BLN enhances them talking to each other.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to reduce capacitive coupling between a BL and a BLN of the same column to reduce their coupling to each other to thereby prevent reduction of the voltage difference, or delta voltage, presented to the differential input terminals of a senseamp.
In accordance with this and other objects of the invention, a memory device is provided that has a pair of digit lines (BL & BLN) formed in a first and a second vertically-spaced horizontal connection layers for a column of memory cells. Each of the digit lines has at least one vertical shift zone in which each digit line shifts between the first and the second vertically-spaced horizontal connection layers. Each of the digit lines has at least one horizontal shift zone formed in the same one of the first and second vertically spaced connection layers such that the horizontal shift zone keeping each digit line in the same connection layer. The digit lines are vertically twisted so that the digit lines do not lie next to each other in the same horizontal plane. The digit lines of the line pair are both vertically and horizontally offset with respect to each other so that one line is in one horizontal connection layer and in one vertical plane while the other line is in the other horizontal connection layer and in another vertical plane. The memory device includes an SRAM memory device.
The vertical shift zone is provided with vertical conductive connections. The vertical shift zone is located in a crossover channel that runs across a number of pairs of digit lines for various columns of SRAM cells. The horizontal shift zone is located in a crossover channel that runs across a number of pairs of digit lines for various columns of SRAM cells. The pair of digit lines are connected to two or more SRAM cells in a column of such cells.
A crossover channel is provided that runs across a number of pairs of digit lines for various columns of SRAM cells. The pairs of digit lines have alternate vertical shift zones and horizontal shift zones formed in the crossover channel.
In one embodiment of the invention the memory cells are 6T SRAM cells with six transistors. Various combinations of vertical shift zones and horizontal shift zones are used. For example, the pair of digit lines can include two vertical shift zones and one horizontal shift zone. The pair of digit lines includes one vertical shift zone an

Affiliated with

Also associated with

Rating

SRAM bit line architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SRAM bit line architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM bit line architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3178122