Amplifiers – With semiconductor amplifying device – Including field effect transistor
Reexamination Certificate
2002-06-21
2003-12-09
Riley, Shawn (Department: 2838)
Amplifiers
With semiconductor amplifying device
Including field effect transistor
C330S253000
Reexamination Certificate
active
06661289
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a Rail-to-Rail voltage-to-current conversion circuit, comprising MOSFETs, and in which the linear operating range has been extended to the power source range, and an OTA (Operational Transconductance Amplifier) using the same. More particularly, the present invention relates to a voltage-to-current conversion circuit, in which the transconductance is kept constant by using two MOSFETs of the same polarity, and an OTA using the same.
Recently, it has become important to reduce the voltage of the power source of an analog integrated circuit composed of MOSFETs, from the general requirements of the reduction in power consumption of semiconductor integrated circuits and in withstand voltage of devices.
An analog-to-digital hybrid circuit is an integrated circuit that is expected to be widely used in the future. In a digital circuit, the power consumption is in proportion to the second power of the power source voltage to be supplied to the circuit and, therefore, reduction in power source voltage is an effective approach to reduce the power consumption. As a result, there is a trend that the power source voltage of a digital circuit is lowered year after year. As the power source voltage of a digital circuit is lowered, that of the part of an analog circuit composed of MOSFETs, which is realized on the same chip, is required to be lower. On the other hand, as the signal processing becomes more complicated, the operating speed of an integrated circuit increases, the semiconductor process becomes finer in order to enable a higher speed operation, and as a result, the withstand voltage of a device is lowered. Therefore, the reduction in power source voltage becomes an unavoidable issue in an integrated circuit using a high-speed processor.
Generally, the reduction in power source voltage in an analog integrated circuit causes a problem that the linear range of an input signal is reduced. Various Rail-to-Rail circuits, in which the linear range of input signal has been extended to that of the positive and negative power source voltage, have been proposed as circuit configurations to solve this problem.
Among the fundamental circuit elements in an analog circuit composed of MOSFETs, there are the voltage-to-current conversion circuit that generates an output current in accordance with an input voltage and the OTA (Operational Transconductance Amplifier) using same.
FIG. 1
is a diagram that shows circuit symbols of an OTA. An OTA circuit
1
puts out an output current Iout in accordance with the difference between two input voltages Vin
1
and Vin
2
. For the above-mentioned voltage-to-current conversion circuit and OTA, the Rail-to-Rail circuit has been proposed.
FIG. 2
is a diagram that shows the configuration of the Rail-to-Rail OTA circuit, which has been disclosed in M. F. Li, U. Dasgupta, X. W. Zhang, Y. C. Lim, “A low-Voltage CMOS OTA with Rail-to-Rail Differential Input Range”, IEEE Trans. Circuit and Systems 1, vol. 47, pp. 1-8, January 2000. As shown schematically, the OTA circuit has extended the linear input range by using in parallel a pOTA circuit
1
p
composed of a p channel MOSFET and an nOTA circuit
1
n
composed of an n channel MOSFET. In this circuit, however, which uses a p channel MOSFET and an n channel MOSFET, the matching of the transconductances of transistors of different polarity is required in order to achieve a linear characteristic.
Takai, Watanabe, Takagi, Fujii, “Rail-to-Rail OTA using Transconductance-Parameter-independent OTA”, ECT-00-94, pp. 73-78, October 2000 has disclosed the configuration in which the transconductance of two input circuits is kept constant by the control voltage generated by using circuits similar to those of the two input circuits, and furthermore, the influence of the operation at the point where the operations of the two input circuits switch is suppressed by using a current selection circuit.
Moreover, Sato, Takagi, Fujii, “Rail-to-Rail OTA using One kind MOSFET's as VCCS”, ECT-00-95, pp. 79-84, October 2000 has disclosed the OTA that has combined a pair of MOSFETs and a MOSFET of the same polarity. Since the OTA is composed of MOSFETs of the same polarity, there is no problem about the matching of transconductances.
SUMMARY OF THE INVENTION
The object of the present invention is to realize a voltage-to-current conversion circuit composed of MOSFETs of the same polarity, which can realize an OTA with Rail-to-Rail with a simpler configuration.
FIG. 3
is a diagram that shows the basic configuration of the voltage-to-current conversion circuit of the present invention. As shown schematically, the voltage-to-current conversion circuit of the present invention is characterized by comprising a first MOSFET
11
, to which a fixed drain-source voltage is applied all the time and which generates a first current signal ID
1
for the input voltage, a second MOSFET
12
, which has the same polarity as that of the first MOSFET
11
, to which the fixed drain-source voltage is applied all the time, and which generates a second current signal ID
2
for the input voltage, which is complementary to the first current signal ID
1
, and a difference current operation circuit
13
that performs the operation to calculate the difference between the first current signal ID
1
and the second current signal ID
2
.
The first MOSFET
11
and the second MOSFET
12
can each be an n channel type or a p channel type as long as they have the same polarity.
There are various modifications for the method to make the first MOSFET
11
and the second MOSFET
12
operate so as to generate current signals complementary to each other.
FIG. 4A
is a diagram that shows the basic configuration in which the sources of the first MOSFET
11
of n channel type and the second MOSFET
12
of n channel type are grounded and a fixed voltage is applied to each drain, and
FIG. 4B
is a diagram that shows the voltage-to-current characteristics of the two MOSFETs.
In this basic configuration, the sources of the first MOSFET
11
and the second MOSFET
12
are grounded, respectively, as shown in
FIG. 4A
, and a voltage VDS is applied to each drain. An input voltage Vin is applied to the gate of the first MOSFET
11
. A gate voltage generation circuit
14
generates and applies a voltage 2VT+VDS−Vin to the gate of the second MOSFET
12
. Here, VT is the threshold voltage of the MOSFET.
First, the variation characteristic of the current ID
1
versus the input voltage Vin of the first MOSFET
11
is described. The operation of the MOSFET can be divided into three regions according to the relationship between a drain-source voltage VDS and a gate-source voltage VGS, as shown in
FIG. 4B
, and a drain current ID in each region is as follows.
Cutoff region: VGS≦VT
ID=0
Saturation region: VT<VGS, VGS−VT<VDS
ID=K (VGS−VT)
2
Non-saturation region: VT<VGS, VDS<VGS−VT
ID=2K (VGS−VT−VDS/2) VDS
Therefore, if the gate-source voltage is assumed to be the input voltage Vin, the linear relationship between the input voltage and the drain current holds only in the non-saturation region.
Since the voltage 2VT+VDS−Vin is applied to the gate of the second MOSFET
12
in
FIG. 4A
, the drain current ID
2
changes as shown in
FIG. 4B
for the input voltage Vin. In other words, the current characteristic is so established that the drain current ID
2
and the drain current ID
1
are symmetrical with respect to the symmetry axis at which the input voltage is VT+VDS/2. Such a relationship between the first MOSFET
11
and the second MOSFET
12
is referred to as the complementary action to each other here, and ID
1
and ID
2
are referred to as the currents complementary to each other.
Therefore, the difference current IO, which is obtained by subtracting the drain current ID
2
of the second MOSFET
12
from the drain current ID
1
of the first MOSFET
11
, is as follows in each region.
Region A: Vin≦VT
First MOSFET
11
: Cutoff region,
Fujii Nobuo
Sato Takahide
Takagi Sigetaka
Wada Kazuyuki
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Riley Shawn
Semiconductor Technology Academic Research Center
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