Computer graphics processing and selective visual display system – Display driving control circuitry – Adjusting display pixel size or pixels per given area
Reexamination Certificate
2000-06-01
2003-02-04
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Adjusting display pixel size or pixels per given area
C345S098000, C345S099000
Reexamination Certificate
active
06515679
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device and, more particularly, to the liquid crystal display device being adaptable for multi-scanning operation and being able to display image data without adding a complicated circuit thereto and deteriorating image qualities inputted thereto.
2. Description of the Related Art
So-called flat display panels are generally used for image displaying devices of late years. While many kinds of flat display panels having various operating principles thereof have been developed, liquid crystal display devices are mostly used for image display devices of computer terminals or the like above all.
In an active-matrix type liquid crystal display device having an active element like a thin film transistor in each of pixels thereof and switching the active element thereby, a liquid crystal driving voltage (a gray scale voltage) is applied to each pixel electrode thereof via each active element, so that cross talks between the pixels can be avoided. Therefore, the active-matrix type liquid crystal display device enables multiple-gray shade display thereby without applying such a special driving method thereto that is applied to a simple matrix type (or, a passive matrix type) liquid crystal display device for preventing cross talks from appearing in the simple-matrix type liquid crystal display device.
FIG. 18
is a block diagram for explaining an exemplified structure of the active matrix type liquid crystal display devices.
FIG. 19
is a timing diagram for explaining various signal waveforms being supplied to a side of the liquid crystal display device shown in
FIG. 18
along a horizontal direction thereof, and
FIG. 20
is a timing diagram for explaining various signal waveforms being supplied to another side thereof along a vertical direction thereof, respectively related to a display control thereof.
The liquid crystal display device comprises an interface board on which an interface circuit is mounted. Receiving various control signals including display data (pixel data) and clock signals being supplied from an external circuit (like a main frame of a computer) to the liquid crystal display device TFT-LCD, the interface circuit applies the pixel data, the clock signals (also denoted simply as “clocks”, hereinafter), and the other various driving voltages to certain portions of the liquid crystal display device.
The interface circuit has a display control device and a power source circuit therein. The display control device outputs and transmits pixel signals to a first pixel of the liquid crystal display device via data bus DB
1
, the other pixel signals to a second pixel thereof via the other data bus DB
2
, clocks D
1
, D
2
to drain drivers being mounted thereon for acquiring the pixel signals into the drain drivers respectively, and a frame starting indication signal FSD and a gate clocks (clock G) to gate drivers being mounted thereon for driving the gate driver, respectively. On the other hand, the power source circuit is constituted by a positive voltage generation circuit PVG, a negative voltage generation circuit NVG, a multiplexer MUX for synthesizing the positive voltage and the negative voltage therein, a counter electrode voltage generation circuit CVG for determining the counter electrode potential, and a gate voltage generation circuit GVG.
A liquid crystal display panel TFT-LCD which constitutes this liquid crystal display device has 1024 pixels juxtaposed along a horizontal direction thereof and 768pixels juxtaposed along a vertical direction thereof. The liquid crystal display panel of this sort belongs to so-called XGA-class being defined by pixel number of 1024×768 thereof. In the interface board for receiving the display data and the control signals sent from the main frame of the computer, red data (R), green data (G), and blue data (B) being received thereat arc divided into groups of two in their respective colors in accordance with every pair of the pixels. For instance, when a red datum, a green datum, and a blue datum corresponding to a first pixel and those corresponding to a second pixel are inputted to the display control device on the interface board as thick arrows in
FIG. 18
show, these data arc grouped into a pair of the red data, a pair of the green data, and a pair of the blue data, and then transmitted to the liquid crystal display panel TFT-LCD through respective data buses DB
1
, DB
2
provided for the first and second pixels within a certain period.
The clock signals (also denoted simply as “Clocks”, hereinafter) defining the aforementioned certain period and having half frequencies as those for respective pixels are sent from the main frame of-the computer through a clock line shown by a thin arrow of FIG.
18
. Concretely, the frequency of the clock becomes 32.5 MHz as a half of 65 MHz.
In a construction of the liquid crystal display panel TFT-LCD, a displaying screen thereof is established as a standard thereof, and drain drivers (TFT-drivers) are disposed in a horizontal direction thereof and connected to drain lines of thin film transistors TFT for supplying voltages for driving liquid crystals to the respective thin film transistors. On the other hand, gate drivers are connected to gate lines thereof so as to supply voltages to respective gates of the thin film transistors TFT during a certain period (one horizontal operation time).
The display control device being constituted by semiconductor integrated circuit (e.g. Large Scale Integrated circuit; LSI) receives display data and control signals sent from the main frame of the computer, and outputs various signals for the two pixels in accordance with the display data and the control signals into the data drivers and the gate drivers. Moreover, the data line for every pixel transmits signal of 18 bits (6 bits for each color of R, G, and B).
A two pixels transmission scheme for transmitting display data for every 2 pixels from the main frame of the computer to the display control device and from the display control device to the drain drivers of the liquid crystal display panel is employed, because the display data cannot be transmitted between the aforementioned apparatuses or the apparatus and the drain drivers by a frequency of 65 MHz as a reference clock for every pixel.
As
FIGS. 19 and 20
shows, a pulse for one horizontal sweeping period based on a horizontal synchronizing signal and a display timing signal is supplied to the gate drivers for every horizontal sweeping (horizontal scanning) so as to apply a voltage to a gate of the thin film transistor TFT. A frame starting indication signal based on a vertical synchronizing signal is also supplied to the gate drivers so as to start to display an image at a first line of the liquid crystal display panel TFT-LCD (a group of pixels juxtaposed in a horizontal direction at an end of a screen thereof) for every one frame period.A signal waveform as Clock (from External) in
FIG. 19
shows a waveform of the aforementioned clock signal inputted from an external circuit (e.g. a main frame of a computer) to the liquid crystal display device thereto.
The positive voltage generation circuit, the negative voltage generation circuit, and the multiplexer being provided in the power source circuit invert directions of electric fields applied to certain liquid crystals for every certain period direction so as to prevent an electric field having a certain direction from being applied to the certain liquid crystals continuously for a long time (Alternation of the liquid crystal driving voltage). The alternation of the liquid crystal driving voltage in this explanation is performed by changing voltages supplied to the drain drivers at either a positive side or a negative side of a counter electrode voltage as a reference for every predetermined period. In this explanation, the alternation is performed in accordance with every frame period. Timings for reversing a polarity of the liquid crystal driving voltage arc controlled by a a
Chang Kent
Hitachi , Ltd.
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