Data processing: measuring – calibrating – or testing – Calibration or correction system – Circuit tuning
Reexamination Certificate
2001-07-03
2003-10-21
Wachsman, Hal (Department: 2857)
Data processing: measuring, calibrating, or testing
Calibration or correction system
Circuit tuning
C702S065000, C326S030000
Reexamination Certificate
active
06636821
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an output driver impedance calibration circuit, and more particularly pertains to an output driver impedance calibration circuit which is used to make a plurality of I/O (input/output) off chip driver characteristics, for a plurality of output driver circuits, alike on the same chip within a tighter tolerance than is otherwise obtainable in the prior art.
2. Discussion of the Prior Art
Integrated circuit communication, chip to chip, relies upon good input-output (I/O) signal integrity. One significant characteristic of an I/O driver circuit that affects the input-output (I/O) signal integrity is its output impedance with respect to the signal line impedance at the system card level. Also, variations of both the I/O driver circuit impedance and the card impedance often become limiting factors in attaining high speed chip to chip communications with good signal integrity. In general, to maximize the transfer of power in a signal, the output impedance of an output driver circuit should match the input impedance of the transmission media connected to the output driver circuit, such as an electrical cable or another circuit or card.
Three major factors which result in variations of the output impedance of an I/O driver circuit are the process technology itself, along with the operating temperature range and the voltage range for the system. Without attempting to control these factors through some calibration scheme, variations in the output impedance with current state-of-the-art CMOS technology with a 100 degree centigrade system operation specification, would generally be no less than +/−18.5% of a 50 ohm target output impedance for an output driver. This variation generally increases as the target output impedance decreases. The effect of the output impedance of an I/O driver circuit on signal integrity of a system is even more important when the magnitude of the output signal swing becomes smaller, as is the trend in the industry.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an output driver impedance calibration circuit.
A further object of the subject invention is the provision of an output driver impedance calibration circuit which can be used to make a plurality of I/O off chip driver characteristics, for a plurality of output driver circuits, alike on the same chip and within a tighter tolerance than is otherwise obtainable in the prior art. One chip might typically have hundreds or thousands of output driver circuits.
To calibrate the output impedance of an input/output driver circuit requires at a minimum:
an external target impedance reference (it could be a multiple of the actual target output impedance);
multiple devices in the output stage of the I/O driver circuit;
a circuit to determine the value of the actual output impedance as compared with its target output impedance;
a scheme to determine when to stop the calibration process.
With these four elements in a calibration process, the I/O impedance can typically be controlled to a +/−6.6% tolerance or better, and significantly benefits the signal integrity of the overall I/O interface.
The calibration circuit is self contained and only requires core logic to toggle a UPDT (update) input at any time a recalibration is required to be updated, for example after a large change in temperature.
The advantages of this approach to calibration are:
no significant/elaborate additional logic is required to operate the calibration;
the number of additional devices in the output stage is easily changed if different tolerances are desired;
the calibration can be performed for both the pull-down circuit and the pull-up circuit at one time, or could be split, and a direct calibration performed separately for each of the pull-down circuit and the pull-up circuit.
The present invention differs from the prior art in that the output device is not binarily weighted, and a logic core macro is used together with an I/O calibration cell to determine when the calibration process is completed, and is self contained in just the I/O calibration cell.
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Wachsman Hal
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