Digital frequency divider with a single shift register

Details Digital frequency divider with a single shift register Digital frequency divider with a single shift register

2002-03-13

2003-10-07

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C377S047000

Reexamination Certificate

active

06630849

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital frequency divider, and in particular to a frequency divider with a shift register.
2. Description of the Related Art
In digital systems, integrated circuits (ICs) or chips are operated by pulses from a clock. In systems such as television receivers or decrypters, there can be many different chips, or regions within a chip, each operating at a different clock frequency. The different regions operating at different frequencies are referred to as “clock domains”. For example, one chip may operate as a master chip in a 166 MHz domain, with another store chip in a 133 MHz domain. In this situation, there is a need for two clock frequencies.
One solution to the problem of providing different clock frequencies is to divide a high speed reference by different amounts.
BRIEF SUMMARY OF THE INVENTION
We have appreciated that the frequency division should introduce a minimum noise into the clocking signal, and involve efficient use of circuitry.
Accordingly, there is provided a digital frequency divider for dividing a clock frequency comprising:
a shift register for storing a bit sequence chosen according to a division factor having one or more tap off points and arranged to provide at least two signals representative of the bit sequence under control of a clock signal at a first frequency;
control logic circuitry having at least two inputs arranged to receive the two signals representative of the bit sequence and arranged to provide at least two output signals; and
a multiplexer arranged to receive the two output signals and to select one of the output signals in turn under control of the clock signal at the first frequency to thereby produce a clock output signal at a second frequency being a division of the first frequency;
wherein the control logic circuitry comprises a detector configured to detect a change in the bit sequence between 0 and 1 and the control logic circuitry being arranged to selectively provide a 0 or 1 as one of the output signals when a change in the bit sequence between 0 to 1 is detected depending on whether even, odd or half integer division is performed.
The detection of changes in the bit sequence in the shift register between 0 and 1 provides information in addition to simply knowing whether the sequence is at 0 or 1 and allows the bit sequence to be chosen for odd, even or half integer division using a single shift register in an efficient manner. The use of a single shift register requires a smaller area of circuitry than a two shift register system.


REFERENCES:
patent: 3890581 (1975-06-01), Stuart et al.
patent: 4234849 (1980-11-01), Crilly, Jr.
patent: 4315166 (1982-02-01), Hughes
patent: 5510742 (1996-04-01), Lemaire
patent: 6393089 (2002-05-01), Maba et al.

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