Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-04-15
2003-11-04
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S261000, C330S263000
Reexamination Certificate
active
06642790
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a differential, complementary amplifier having two complementary amplifier paths, each including a p-channel transistor and an n-channel transistor connected in series. Amplifiers of this type serve for amplifying differential analog or digital input signals. They have a wide range of application and are suitable, in particular, for amplifying high-frequency signals with data rates up to the Gbit/s range.
U.S. Pat. No. 4,937,476 discloses a differential amplifier having two amplifier paths that are arranged in parallel and that each have a pair of CMOS transistors. A third pair of CMOS transistors controls the current supply for the two amplifier paths and sets the operating point thereof. To that end, the output of the drain terminals—connected to one another—of the first amplifier path is connected to the gate terminals of the third CMS transistor pair. The known amplifier makes an output voltage available at the output of the second amplifier path for a differential voltage present at the gate terminals of the two amplifier paths.
U.S. Pat. No. 4,958,133 describes a differential, complementary amplifier having CMOS amplifier paths arranged in parallel. An improved negative feedback is described that provides a high degree of common-mode rejection and a high voltage gain for differential signals.
In the differential amplifiers disclosed in the two documents mentioned, one path of the amplifier always functions solely to stabilize the operating-point and the other path of the amplifier serves as the actual amplifier. As a result, the gain is limited in the case of a relatively large current consumption. Moreover, the abovementioned amplifier circuits in each case have only a “single ended” output. This prevents the use of a simple series circuit with a second differential amplifier stage.
A further differential, complementary amplifier having two amplifier paths is described in U.S. Pat. No. 6,028,467.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a differential, complementary amplifier which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide a differential, complementary amplifier that provides a relatively high gain in conjunction with high bandwidth and low current consumption and that also enables a simple interconnection of a plurality of amplifier stages.
With the foregoing and other objects in view there is provided, in accordance with the invention, a differential, complementary amplifier including: a first complementary MOSFET amplifier path including a p-channel transistor and an n-channel transistor connected in series; a second complementary MOSFET amplifier path including a p-channel transistor and an n-channel transistor connected in series; a first load resistor and a second load resistor; and a node. The second amplifier path is operated in an opposite direction relative to the first amplifier path. The output of the first amplifier path and the output of the second amplifier path form a differential output. The first load resistor connects the output of the first amplifier path to the node. The second load resistor connects the output of the second amplifier path to the node. The operating point of the first amplifier path and the second amplifier path is set by a voltage present at the node.
In accordance with an added feature of the invention, the first amplifier path and the second amplifier path are driven by half of the operating voltage.
In accordance with an additional feature of the invention, the first amplifier path and the second amplifier path have a bandwidth that is variable by varying the first load resistor and the second load resistor.
In accordance with another feature of the invention, there is provided, at least a first FET control transistor and a second FET control transistor for controlling a current supplied to the first amplifier path and to the second amplifier path. The first FET control transistor has a gate terminal connected to the node. The second FET control transistor has a gate terminal connected to the node. The operating point of the first amplifier path and the second amplifier path is set by setting a voltage on the gate of the first FET control transistor and a voltage on the gate of the second FET control transistor.
In accordance with another added feature of the invention, the first FET control transistor is a p-channel control transistor; the second FET control transistor is an n-channel control transistor; and the first FET control transistor and the second FET control transistor are connected in series and form a complementary MOSFET transistor pair.
In accordance with another additional feature of the invention, there is provided, a terminal for receiving an operating voltage; and a ground terminal. The p-channel control transistor has a source terminal connected to the terminal for receiving the operating voltage. The n-channel control transistor has a source terminal connected to the ground terminal. The p-channel control transistor has a drain terminal. The n-channel control transistor has a drain terminal. The first amplifier path and the second amplifier path are configured between the drain terminal of the p-channel control transistor and the drain terminal of the n-channel control transistor.
In accordance with a further feature of the invention, the p-channel transistor of the first amplifier path has a source terminal; the p-channel transistor of the second amplifier path has a source terminal; the n-channel transistor of the first amplifier path has a source terminal; the n-channel transistor of the second amplifier path has a source terminal; the drain terminal of the p-channel control transistor is connected to the source terminal of the p-channel transistor of the first amplifier path and to the source terminal of the p-channel transistor of the second amplifier path; and the drain terminal of the n-channel control transistor is connected to the source terminal of the n-channel transistor of the first amplifier path and to the source terminal of the n-channel transistor of the second amplifier path.
In accordance with a further added feature of the invention, the first FET control transistor and the second FET control transistor are operated in a triode region.
In accordance with a further additional feature of the invention, the p-channel transistor of the first amplifier path and the p-channel transistor of the second amplifier path are identically constructed; and the n-channel transistor of the first amplifier path and the n-channel transistor of the second amplifier path are identically constructed.
In accordance with yet an added feature of the invention, there is provided a capacitor coupled to the node.
In accordance with yet an additional feature of the invention, there is provided, at least a first FET control transistor and a second FET control transistor for controlling a current supplied to the first amplifier path and to the second amplifier path. The first FET control transistor has a gate terminal, and the second FET control transistor has a gate terminal. A first low-pass filter connects the node to the gate terminal of the first control transistor, and a second low-pass filter connects the node to the gate terminal of the second control transistor.
In accordance with yet another feature of the invention, there is provided, at least a first FET control transistor and a second FET control transistor for controlling a current supplied to the first amplifier path and to the second amplifier path; a first current mirror circuit including a MOSFET transistor having an input connected to the node; and a second current mirror circuit including a MOSFET transistor having an input connected to the node. The first control transistor has a source terminal, and the second control transistor has a source terminal. The MOSFET transistor of the first current mirror circuit has an output con
Schrödinger Karl
Stimma Jaro
Infineon - Technologies AG
Locher Ralph E.
Nguyen Khanh V.
Pascal Robert
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