NULL convention logic system

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

3649361, G06F 100

Patent

active

056642121

ABSTRACT:
A Null convention logic system for processing NULL convention signals is comprised of interconnected processing elements. NULL convention signals can assume at least a first meaningful value indicating data and a NULL value which has no data significance. Processing elements receive a plurality of NULL convention signals and produce a meaningful output data value when the number of meaningful input data values exceeds a threshold number. The gates assert a NULL output when all inputs are in the NULL state. Processing elements exhibit hysteresis such that, as the number of meaningful input values falls below the threshold number, the element holds a meaningful output value (or a non-data non-NULL value) until all inputs are in the NULL state. The threshold number may be less than the total number of inputs. Groups of elements may be interconnected, and thresholds selected, to perform logic and other processing functions asynchronously on meaningful signal values.

REFERENCES:
patent: 4845653 (1989-07-01), Furtck
Tadashi Shibata & Tadahiro Ohmi, A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations, IEEE Transactions On Electron Devices, Dec. 1992, vol. 39, No. 6, pp. 1444-1455.
Mark Edward Dean, Strip: A Self-Timed Risc Processor, Jun. 1992.
Daniel Hampel & Robert Winder, Threshold Logic, IEEE Spectrum, Apr. 1971, pp. 32-39.
Janusz A. Brzozowski & Carl-Johan H. Seger, Asynchronous Circuits--Monographs in Computer Science, Springer-Verlag New York, Inc., 1995, New York, NY.
M.R. Greenstreet, T.E. Williams, and J. Staunstrup, Self-Timed Iteration, Elsevier Science Publishers B.V. (North-Holland), IFIP, 1988, pp. 309-322.
Teresa H.-Y. Meng, Robert W. Brodersen, and David G. Messerschmitt, Automatic Synthesis of Asynchronous Circuits from High-Level Specifications, IEEE Transactions on Computer-Aided Design, vol. 8, No. 11, Nov. 1989, pp. 1185-1205.
Ted Williams, Latency and Throughput Tradeoffs in Self-Timed Speed-Independent Pipelines and Rings, Stanford University Technical Report No. CSL-TR-91-482, May 1991.
Jens Sparso and Jorgen Staunstrup, Delay-insensitive multi-ring structures, Integration, the VLSI Journal 15, 1993, Elsevier Science Publishers B.V., pp. 313-340.
Tzyh-Yung Wuu and Sarma B.K. Vrudhula, A Design of a Fast and Area Efficient Multi-Input Muller C-element, IEEE Transactions on VLSI Systems, vol. 1, No. 2, Jun. 1993, pp. 215-219.
Marc Renaudin and Bachar El Hassan, The Design of Fast Asynchronous Adder Structures and Their Implementation Using D.C.V.S. Logic, Int'l. Symposium on Circuits & Systems, vol. 4, 1994, pp. 291-294.
Richard G. Burford, Xingcha Fan and Neil W. Bergmann, An 180 Mhz 16 bit Multiplier Using Asynchronous Logic Design Techniques, IEEE 1994 Custom Integrated Circuits Conference, pp. 215-218.
Ted Williams, Self-Timed Rings and Their Application to Division, Stanford University Technical Report No. CSL-TR-91-482, May 1991.
David E. Muller, Asynchronous Logics and Application to Information Processing, Stanford University Press, Switching Theory In Space Technology, pp. 289-297, 1963.
Narinder Pal Singh, A Design Methodology For Self-Timed Systems, Massachusetts Institute of Technology, MIT/LCS/TR-258, Feb. 1981.
T.S. Anatharaman, A Delay Insensitive Regular Expression Recognizer, Dept. of Computer Science, Carnegie-Mellon University, CMU-CS-89-109, Jan. 1989.
Jens Sparso, et al., Design of Delay Insensitive Circuits Using Multi-Ring Structures, European Design Automation Conference, IEEE 0-8186-2780, pp. 15-20, Aug. 1992.
Lawrence G. Heller, et al., Cascode Voltage Switch Logic: A Different CMOS Logic Family, ISSCC 84 Digest of Technical Papers, IEEE, pp. 16-17, Feb. 1984.
Lars S. Nielsen and Jens Sparso, A Low-Power Asynchronous Data-Path For A FIR Filter Bank, IEEE 0-8186-7298-Jun. 1996, pp. 197-207, Jun. 1996.
Stephen H. Unger, Asynchronous Sequential Switching Circuits, 1969, pp. 221, 229.
Carver Mead, Lynn Conway, Introduction to VLSI Systems, 1980, pp. 242-262.
Ivan E. Sutherland, Micropipelines, Jun. 1989, vol. 32, No. 6, Communications of the ACM.
Wojcik et al., On the Design of Three Valued Asynchronous Module, IEEE Transactions on Computers, vol. C-29, No. 10, Oct. 1980, pp. 889-898.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

NULL convention logic system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with NULL convention logic system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and NULL convention logic system will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-317310

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.