Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2001-03-27
2003-10-07
Tokar, Michael (Department: 2819)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S255000, C330S261000, C330S264000
Reexamination Certificate
active
06630863
ABSTRACT:
Japanese patent application No. 2000-98917 filed on Mar. 31, 2000 is hereby incorporated by reference in its entirety.
TECHNICAL FIELD
The present invention relates to a differential amplifier having two sets of differential amplifier circuits, a semiconductor device, a power supply circuit, and electronic equipment using the same.
BACKGROUND
A differential amplifier is shown in
FIG. 8
, which device has two, first and second differential amplifier circuits
210
,
230
. The first and second differential amplifier circuits
210
,
230
are designed to receive first and second input voltages V
IN1
, V
IN2
which have an offset therebetween. A P-type MOS transistor
250
is provided at the rear stage of the first differential amplifier circuit
210
, which transistor is driven by a first signal S
1
coming from the first differential amplifier circuit
210
. Similarly, an N-type MOS transistor
252
is provided at the rear stage of the second differential amplifier circuit
230
, which transistor is driven by a second signal S
2
from the second differential amplifier circuit
230
. These PMOS transistor
250
and NMOS transistor
252
are operable to pull together thus defining an output voltage V
OUT
.
As shown in
FIG. 8
the first differential amplifier circuit
210
includes a P-type MOS transistor
212
and a P-type MOS transistor
214
that constitutes a current-mirror circuit together with the PMOS transistor
212
.
The second differential amplifier circuit
230
includes an N-type MOS transistor
232
and an N-type MOS transistor
234
that makes up a current-mirror circuit together with the NMOS transistor
232
.
The first differential amplifier circuit
210
further has an NMOS transistor
216
that is serially connected to the PMOS transistor
212
between power supply voltages V
DD
, V
SS
, and an NMOS transistor
218
as connected in series to the PMOS transistor
214
between the power supply voltages V
DD
, V
SS
. Additionally the NMOS transistors
216
,
218
are coupled through a constant current source
220
to the power supply voltage V
SS
. These NMOS transistors
216
,
218
are the same as each other both in size and in ability, and thus constitute a differential pair.
Similarly the second differential amplifier circuit
230
has a PMOS transistor
236
that is serially connected to the NMOS transistor
232
between the power supply voltages V
DD
, V
SS
and a PMOS transistor
238
as series-connected to the NMOS transistor
234
between power supply voltages V
DD
, V
SS
. The PMOS transistors
236
,
238
are coupled to power supply voltage V
DD
via a constant current source
240
. These PMOS transistors
236
,
238
are the same in size and ability as each other, thus making up a differential pair.
SUMMARY
According to one embodiment, there is provided a differential amplifier comprising:
a first differential amplifier circuit which operates based on a first input voltage and includes a first transistor of a primary conductivity type and a second transistor of the primary conductivity type which makes up a differential pair with the first transistor of the primary conductivity type;
a second differential amplifier circuit which operates based on a second input voltage and includes a first transistor of a secondary conductivity type and a second transistor of the secondary conductivity type which makes up a differential pair with the first transistor of the secondary conductivity type;
a third transistor of the secondary conductivity type which operates based on a first signal from the first differential amplifier circuit;
a third transistor of the primary conductivity type which is serially connected to the third transistor of the secondary conductivity type and operates based on a second signal from the second differential amplifier circuit; and
a voltage control circuit (first control circuit) which controls a voltage of a control terminal of the third transistor of the secondary conductivity type, based on a third signal from the second differential amplifier circuit,
wherein a voltage between the third transistor of the secondary conductivity type and the third transistor of the primary conductivity type is used as an output voltage.
According to another embodiment, there is provided a differential amplifier in which the first voltage control circuit is replaced by a second voltage control circuit which controls a voltage of a control terminal of the third transistor of the primary conductivity type based on a fourth signal from the first differential amplifier circuit.
According to further embodiment, there is provided a differential amplifier comprising both the first and second voltage control circuits described above. This makes it possible to accelerate the operation of both the third transistor of the secondary conductivity type and the third transistor of the primary conductivity type.
According to yet another embodiment, there is provided a power supply circuit comprising at least one such differential amplifier, or electronic equipment comprising such a power supply circuit.
REFERENCES:
patent: 4284958 (1981-08-01), Pryor et al.
patent: 5216382 (1993-06-01), Ito
patent: 5266887 (1993-11-01), Smith
patent: 5621357 (1997-04-01), Botti et al.
patent: 5670910 (1997-09-01), Kato
patent: 5751186 (1998-05-01), Nakao
patent: 5841321 (1998-11-01), Miyake et al.
patent: 6100762 (2000-08-01), Kato
patent: 6259322 (2001-07-01), Muza
patent: 6359512 (2002-03-01), Ivanov et al.
patent: 10-233636 (1998-09-01), None
patent: 11-88076 (1999-03-01), None
patent: 2000-0004448 (2000-01-01), None
Cordaro, “Complementary Fet Differential Amplifier”, IBM Technical Disclosure Bulletin, IBM Corp., New York, vol. 16, No. 10, Mar. 1974, pp. 3227-3228, XP002103389.
Callewaert et al., “Class AB CMOS Amplifiers with High Efficiency”, IEEE Journal of Solid-State Circuits, IEEE Inc., New York, vol. 25, No. 3, Jun. 1, 1990, pp. 684-691, XP000140198.
U.S. application Ser. No. 09/817,193, Tsuchiya, filed Mar. 27, 2001, pending.
Nguyen Khai
Tokar Michael
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