Multiplex communications – Communication techniques for information carried in plural... – Adaptive
Reexamination Certificate
1999-06-04
2003-02-04
Chin, Wellington (Department: 2664)
Multiplex communications
Communication techniques for information carried in plural...
Adaptive
C370S502000
Reexamination Certificate
active
06516001
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a device for obtaining a DS-N data output asynchronous to SONET (synchronous optical network) from SONET data input.
BACKGROUND OF THE INVENTION
Since the transmission rate of SONET is on the basis of 51.84 Mbps and the transmission rate of DS-N is on the basis of 64 kbps, they are numerically in integer-fold relation to each other. However, since the respective clock frequencies incur errors, SONET data become asynchronous to DS-N data. Therefore, to obtain a DS-N data output from SONET data input, a special device is required.
Japanese patent application laid-open No. 6-204962 (1994) (hereinafter referred to as ‘prior art
1
’) discloses a device and a method for desynchronizing SONET to DS-N signal.
FIG. 1
is a block diagram showing the circuit composition of the device in prior art
1
. SONET data input is written into a data buffer
1
and is then output as DS-N data output from the data buffer
1
.
A write address (WADR) to determine the write position of SONET data in the data buffer
1
is supplied from a write address counter
2
that counts SONET clock.
An address position to read DS-N data from the data buffer
1
is supplied from a read address counter
3
.
SONET data input is sequentially written into a position indicated by the write address counter
2
, and after delaying a proper time, a count value of the read address counter
3
corresponds to a previous count value of the write address counter
2
, thereby data written previously is read sequentially.
The preferable amount of delay of the count value of the read address counter
3
to the count value of the write address counter
2
is half of the whole amount of addresses.
With such a setting, both a risk that the count value of the read address counter
3
is so advanced that it passes the count value of the write address counter
2
and a risk that the count value of the read address counter
3
is so delayed that it is passed by the count value of the write address counter
2
(taking a round within all addresses) can be made minimum.
To keep such a relationship, the frequency of clock DSCLK counted by the read address counter
3
is feedback-controlled.
A deviation of delay of the count value of the read address counter
3
to the count value of the write address counter
2
from the preferable amount is stored into a buffer offset register
4
, as an offset value. This value is updated by every timing pulse UPDATE generated by a control loop timer
5
. A micro-controller
6
is fed with the content (OFFSET) of the buffer offset register
4
as an error signal, and then generates a frequency adjusting (control) signal from this error signal.
FIG. 2
is a block diagram showing calculations in the micro-controller
6
, where
60
,
63
and
64
are multipliers,
65
is an adder,
61
is an integration circuit and
62
is a differential circuit.
In so-called PDI control that an error signal e(nt) is input from the buffer offset register
4
and then a frequency adjusting (control) signal m(nt) is output to a DDS (direct digital synthesizer) circuit
7
, m(nt) is given by:
m
(
nt
)=
K
p
e
(
nt
)+
K
I
∫e
(
nt
)
dt+K
D
de
(
nt
)/
dt
(1)
where the integration part and differential part are placed to enhance the control characteristic and K
D
=0, K
I
=0 or K
D
=K
I
=0 may be set. In prior art
1
, the fuzzy control can be also employed.
FIG. 3
is a block diagram showing the composition of the DDS circuit
7
. In
FIG. 3
,
70
a
is a center frequency register,
70
b
is an adder,
71
a
is an adder,
71
b
is an accumulator,
72
is a look-up table ROM (read-only memory),
73
is DAC (digital-to-analog converter) and
74
is LPF (low-pass filter).
The error signal e(nt) can have a positive or negative value, therefore the frequency control signal m(nt) can have a positive or negative value. However, it is necessary for the DDS circuit
7
to avoid that an accumulated value by the adder
71
a
and accumulator
71
b
becomes negative. With the center frequency register
70
a
and the adder
70
a
, if the value of frequency control signal is 0, then the DDS circuit generates the center frequency.
When the value of frequency control signal is positive, the DDS circuit generates a frequency higher than the center frequency, and when the value of frequency control signal is negative, the DDS circuit generates a frequency lower than the center frequency.
Namely, the content of the center frequency register
70
a
and the value of frequency control signal are added by the adder
70
b
, and then a sine wave with a frequency proportional to the output of the adder
70
b
(the content of the center frequency register
70
a
is determined so that this output always becomes positive) is generated.
Provided that the accumulator
71
b
is modulo-N, the content of the accumulator
71
b
is an integer value of 0, 1, 2, . . . , j, . . . , N−1, and increases by the output value of the adder
70
b
every time DDS reference clock generates.
The look-up table ROM
72
stores a value of sin 2&pgr;j/N, as data, at the address position corresponding to output j of the accumulator
71
b
. Therefore, the output of ROM
72
is formed into a sine wave and its frequency is proportional to the output of the adder
70
b
. This is converted into analog signal by DAC
73
, smoothed by LPF
74
, output as clock CLK
1
.
Referring back to
FIG. 1
, clock CLK
1
is frequency-mixed (in this case, an added frequency is extracted) by the output frequency of a local oscillator
11
and a double-balanced mixer
10
. Then, through a bandpass filter
9
and a logic level converter
12
, it is counted by the read address counter
3
, as clock DSCLK for the read address counter
3
.
By the feedback circuit described above, the difference between WADR and RADR is kept at a given value.
FIG. 4
is a flow chart showing the steps of operation described above. At step
101
the components are initialized, at step
102
waiting for a firmware to come to ‘online mode’, at step
103
setting the initial frequency. For example, the value of frequency control signal is set 0.
At step
104
the interrupt is allowed, at step
105
waiting for the control loop timer to interrupt with UPDATE signal.
When the interrupt occurs, the buffer offset register
4
is read (step
106
A). At this time, it is checked whether a spill occurs or not (step
106
B).
The spill means generalizing a case that the count value of the read address counter
3
is so advanced that it passes the count value of the write address counter
2
and a case that the count value of the read address counter
3
is so delayed that it is passed by the count value of the write address counter
2
(taking a round within all addresses).
When the spill occurs, the buffer offset register
4
is reset (step
106
C), returned to step
105
.
When the spill does not occur, at step
107
the average offset and average slope are calculated newly. The calculation of average offset is the operation of the integration circuit
61
in
FIG. 2
, and the calculation of average slope is the operation of the differential circuit
62
in FIG.
2
.
Then, step
108
conducting the calculation of expression (1) described above, at step
109
sending a newly calculated frequency control signal to DDS, returning to step
105
, waiting for the next interrupt.
The device in prior art
1
is thus composed, and when generating a frequency control signal m(nt) from an error signal e(nt), the frequency control signal m(nt) is determined uniformly calculating expression (1) without taking the largeness of absolute value of e(nt) into account. Therefore, when e(nt) is varied abruptly, there occurs a problem that time required until the frequency of clock DSCLK reaches a final value becomes too long. Since e(nt) is varied abruptly when switching DS-N, this problem is serious.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a device for converting SONET data input into DS-N data output asyn
Dickstein Shapiro Morin & Oshinsky LLP.
NEC Corporation
Pham Brenda
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