Electric lamp and discharge devices – With luminescent solid or liquid material – Vacuum-type tube
Reexamination Certificate
1999-07-20
2003-11-18
Patel, Vip (Department: 2879)
Electric lamp and discharge devices
With luminescent solid or liquid material
Vacuum-type tube
C313S495000, C313S309000, C313S351000
Reexamination Certificate
active
06650043
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an improved multilayer conductor for use with electrical circuits. Multilayer conductors constructed according to the invention may be used advantageously in field emission displays (FEDs) as well as in other integrated circuits.
BACKGROUND OF THE INVENTION
Since a preferred use of the invention is in FEDs, the background of FEDs will now be discussed.
FIG. 1A
shows a cross sectional view of a portion of a prior art FED
100
. FED
100
includes a cathode, or baseplate,
102
and an anode, or faceplate,
104
. Baseplate
102
includes a substrate
106
, a plurality of conical field emitters
108
, a dielectric layer
110
, and a conductive grid layer
112
. Dielectric layer
110
is disposed over substrate
106
, and grid layer
112
is disposed over dielectric layer
110
. Dielectric layer
110
defines a plurality of cylindrical, or bowl shaped, void regions
114
, and each emitter
108
is disposed over substrate
106
in one of the void regions
114
. Grid layer
112
defines a plurality of circular apertures
116
. Each aperture
116
corresponds to, and overlies, one of the void regions
114
. A single emitter
108
is disposed underneath each of the apertures
116
. The apertures
116
are positioned so that (1) the grid layer
112
does not obstruct a path
117
between the upper tips of the emitters
108
and the faceplate
104
and (2) a portion of the grid layer
112
is proximal to the upper tip of each emitter
108
. Baseplate
102
also includes a plurality of conductive column lines
118
disposed between emitters
108
and substrate
106
. In
FIG. 1A
, portions of three column lines are shown as lines
118
a
,
118
b
, and
118
c.
FIG. 1B
shows a magnified top view of a portion of baseplate
102
. The grid layer
112
is arranged as a set of conductive row lines (three of which
112
a
,
112
b
,
112
c
are shown) with the row lines being perpendicular to the underlying column lines
118
.
Referring again to
FIG. 1A
, faceplate
104
includes a transparent glass plate
120
, a transparent conductor
122
, and a phosphor layer
124
. Transparent conductor
122
is disposed on one major surface of glass plate
120
, and phosphor layer
124
is disposed on transparent conductor
122
. Faceplate
104
also includes a black matrix (not shown). The black matrix divides the phosphor layer into an array, or matrix, of pixels. The location of one of the pixels
160
is indicated in FIG.
1
A. Pixel
160
could be a single pixel of a black and white display or alternatively could form a single red, green, or blue dot of a color (RGB) display. The faceplate
104
and baseplate
102
are spaced apart from one another and are disposed so that the phosphor layer
124
is proximal to the grid layer
112
.
The collection of emitters
108
disposed at the intersection of a single row line and a single column line are used to control illumination of a single pixel of the display
100
. For example, as shown in
FIG. 1B
, a group
162
of approximately sixteen emitters
108
(disposed within the approximately sixteen apertures
116
) is located at the intersection of row line
112
b
(of the grid layer
112
) and column line
118
b
. This group
162
of emitters is used to control illumination of pixel
160
(indicated in FIG.
1
A). Typical displays often use hundreds or thousands of emitters to control illumination of a single pixel. However, for convenience of illustration,
FIG. 1B
shows only about sixteen emitters per pixel.
Referring again to
FIG. 1A
, FED
100
also includes a plurality of spacers
130
disposed between faceplate
104
and baseplate
102
. The spacers
130
maintain the orientation between baseplate
102
and faceplate
104
so that the baseplate and faceplate are substantially parallel to one another. Outer walls (not shown) seal the outer periphery of FED
100
and the space between baseplate
102
and faceplate
104
is substantially evacuated (creating a vacuum of about 10
−7
Torr). Since the space between faceplate
104
and baseplate
102
is substantially evacuated, atmospheric pressure tends to press baseplate
102
and faceplate
104
together. Spacers
130
resist this pressure and maintain the substantially parallel, spaced apart, orientation of baseplate
102
and faceplate
104
.
FED
100
also includes a power supply
140
for (1) charging the transparent conductor
122
to a highly positive voltage (e.g., 1,500 Volts); (2) selectively charging rows of the conductive grid layer
112
to a positive voltage (e.g., 30 Volts); and (3) selectively charging the conductive column lines
118
to a negative voltage (e.g., −10 Volts).
In operation, voltages applied to the column lines
118
, the rows of the grid layer
112
, and the transparent conductor
122
selectively cause emitters
108
to emit electrons
150
that travel along path
117
towards, and impact on, phosphor layer
124
. Incident electrons on phosphor layer
124
cause phosphor layer
124
to emit photons and thereby generate a visible display on faceplate
104
. Power supply
140
generates a visible display by periodically illuminating (or not illuminating) the pixels in the display matrix. Normally, power supply
140
continuously charges transparent conductor
122
to the highly positive voltage. Power supply
140
illuminates a single pixel by simultaneously applying the negative and positive voltages to that pixel's column and row lines, respectively.
The column lines
118
and the rows of the grid layer
112
are typically made from strips of aluminum. Although aluminum has been used for many years to form conductors in FEDs as well as in other types of integrated circuits, aluminum has several undesirable characteristics. For example, aluminum is not physically stable over long periods of time when it is disposed adjacent to silicon-based materials. Aluminum has a tendency to slowly diffuse into adjacent silicon-based materials and form structures known as “hillocks”. Since almost every layer of modern integrated circuits is silicon-based (e.g., silicon oxide, silicon nitride, single crystal silicon, polycrystalline silicon, or glass), the tendency of aluminum to diffuse into silicon-based layers is a serious drawback to its use. As used herein, the term “silicon-based” shall mean any material that includes silicon, either in elemental form or in the form of one or more compounds.
FIGS. 2A
,
2
B,
2
C,
2
D illustrate the undesirable tendency of aluminum for forming hillocks in adjacent silicon-based layers.
FIG. 2A
shows a top view of a structure
200
and
FIG. 2B
shows a magnified sectional view of structure
200
taken in a direction indicated by line
2
B—
2
B as shown in FIG.
2
A. Structure
200
includes four conductive aluminum lines
210
,
211
,
212
,
213
disposed between, and in physical contact with, a lower silicon-based layer
202
and an upper silicon-based layer
204
. It will be appreciated that structure
200
could represent a small portion of almost any integrated circuit.
The lower silicon-based layer
202
could comprise a substrate made for example from single crystal silicon, polycrystalline silicon, or glass. More commonly, both upper and lower silicon-based layers
202
,
204
would be silicon-based insulators made for example from silicon oxide or silicon nitride. In this case, additional layers (e.g., silicon-based layers containing active devices such as transistors) could be disposed both above and below the upper and lower silicon-based layers
202
,
204
. It will be further appreciated that aluminum lines
210
-
213
could comprise a small portion of a bus (e.g., an address bus or a data bus) in a memory or processor chip. Alternatively, aluminum lines
210
-
213
could comprise a portion of the column lines in a FED. In that case, lower silicon-based layer
202
would be part of the baseplate
102
(as shown in FIG.
1
A). In typical applications the width W of the conductive lines is about 2,000 Angstroms and the thickness T of the conductive lines is
Guharay Karabi
Hale and Dorr LLP
Micro)n Technology, Inc.
Patel Vip
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