Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-11-26
2003-12-30
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000
Reexamination Certificate
active
06670944
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a shift register circuit including a plurality of stages connected in a cascaded fashion, a driving circuit for driving an electrooptical device including a plurality of pixels, an electrooptical device using such a driving circuit, and an electronic apparatus employing such an electrooptical device as a display device.
2. Description of Related Art
A conventional electrooptical device, such as an active matrix liquid crystal display device, consists mainly of a device substrate on which pixel electrodes together with switching elements are formed in a matrix fashion, an opposite substrate on which a color filter is formed, and a liquid crystal disposed in a space between the two substrates. In this structure, if a scanning signal (selection voltage) is applied to a switching element via a scanning line, the switching element is brought into a conductive state. When the switching element is in the conductive state, if an image signal is applied to a pixel electrode via a data line, an arbitrary charge is stored in the liquid crystal layer between that pixel electrode and an opposite electrode (common electrode). After storing the charge, a non-selection voltage is applied to the switching element so as to turn it off. If the liquid crystal layer has a sufficiently high resistance, the charge is maintained in the liquid crystal layer even after the switching element has been turned off. The orientation of the liquid crystal can be controlled for each pixel by controlling the amount of charge stored via the respective switching elements. Thus, desired information can be displayed.
In this technique, the operation of storing the charge into the liquid crystal layer for each pixel is required only in a particular period. This allows the liquid crystal display device to be driven in a time division multiplexing fashion in which scanning lines and data lines are used in common for a plurality of pixels, as described below. That is, first, the scanning lines are sequentially selected by a scanning line driving circuit. Second, during a selection period in which one scanning line is selected, one or more data lines are selected by a data line driving circuit. Third, a sampled image signal is applied to the selected data line(s).
The scanning line driving circuit and the data line driving circuit are generally similar in construction to each other. For example, in a typical construction as shown in
FIG. 19
, the data line driving circuit includes a shift register circuit
1560
consisting of a plurality of unit circuits connected in a cascade fashion. A transfer start pulse DX is applied to the shift register circuit
1560
at the start of each horizontal scanning period. The transfer start pulse DX is transferred through the cascaded unit circuits from one to another in response to a clock signal CLX and an inverted clock signal CLX
INV
, and sampling pulses S
1
-Sn to be used to sample a data signal are output one after another from the unit circuits. Similarly, in a typical scanning line driving circuit, a transfer start pulse DY is applied, instead of the transfer start pulse DX, to a shift register circuit at the start of each vertical scanning period, and instead of the clock signal CLX and the inverted clock signal CLX
INV
, a clock signal CLY and an inverted clock signal DLY
INV
are supplied every horizontal period.
In the case of an active matrix liquid crystal display device including switching elements each formed of thin film transistors (TFTs) and also including a built-in driving circuit formed of TFTs for driving the switching elements, a rather high voltage of about 12 V is required as the operating voltage. As a result, a similar voltage is also required for the scanning line driving circuit and the data line driving circuit which perform logic operations in synchronization with clock signals. In contrast, a timing generator (not shown in
FIG. 19
) for supplying clock signals to a liquid crystal display panel is generally formed of a CMOS circuit whose output voltage is about 3 to 5 V. To handle the voltage difference, the data line driving circuit
158
includes, as shown in
FIG. 19
, level shifters (level conversion circuits)
1512
and
1522
as clock interfaces disposed at the input stage to convert a signal with a small logic swing of 0 to 3 V to a signal with a large logic swing of 0 to 12 V. That is, in the conventional scanning line driving circuit and data line driving circuit, the signal with the small logic swing generated by the timing generator is supplied to the unit circuits of the shift register circuit
1560
after being converted by the level shifter into a signal with the large logic swing.
In recent years, electrooptical devices, in particular active matrix liquid crystal display devices widely used in portable electronic apparatuses, are required to operate with very low power consumption. Of various circuits in the electrooptical device, the data line driving circuit
158
operates in synchronization with a highest-frequency clock signal and needs the greatest power consumption. Therefore, a key point to reduce the power consumption of the electrooptical device is to reduce the power consumption of the data line driving circuit
158
.
In the conventional data line driving circuit
158
described above, the clock signal CLX and the inverted clock signal CLX
INV
level-shifted by the level shifters
1512
and
1522
are supplied to the unit circuits at the respective stages of the shift register circuit
1560
. However, in this technique, the lines A and B which the clock signals with the large logic swing are supplied tend to become long. As a result, the capacitance associated with the lines A and B becomes large.
In general, electric power consumed by a capacitive load increases in proportion to the capacitance C of the capacitor, the frequency f of a signal supplied to the capacitor, and the square of the voltage V of the signal. Because the lines A and B serve to transmit the clock signals with the large logic swing along a large distance, the lines A and B have large capacitance C, and large voltages V are applied to the large capacitance C. Therefore, large electric power is consumed when the clock signals with the large logic swing are applied to the capacitance associated with the lines A and B.
SUMMARY OF THE INVENTION
In view of the above, it is one aspect of the present invention to provide a shift register circuit applicable to a data line driving circuit and capable of operating with small power consumption, a driving circuit using such a shift register circuit for driving an electrooptical device, an electrooptical device, and an electronic apparatus using the electrooptical device as a display device.
According to an aspect of the invention, there is provided a shift register circuit including a plurality of stages connected in a cascaded fashion for sequentially transferring an input signal in response to a clock signal with a large amplitude. The shift register circuit may further include a plurality of level shifting circuits each coupled with one or more stages of the shift register circuit, each level shifting circuit serving to convert a clock signal with a small amplitude to a clock signal with a large amplitude and supply the resultant clock signal to the one or more stages coupled with each level shifting circuit.
In this shift register circuit constructed in the above-described manner, each level shifting circuit coupled with one or more stages of the shift register circuit supplies a level-shifted clock signal with the large amplitude to the one or more stages coupled with that level shifting circuit. This allows a reduction in the length of lines used to supply the clock signal with the large amplitude compared with the conventional technique in which the clock signal with the large amplitude is supplied by one level shifting circuit to all stages. As a result, the capacitance associated with the lines used to supplying the clock signa
Eisen Alexander
Hjerpe Richard
Oliff & Berridg,e PLC
Seiko Epson Corporation
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