Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-09-13

2003-02-04

Mai, Son (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S154000, C365S189040, C365S190000

Reexamination Certificate

active

06515887

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-290933, filed Sep. 25, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention concerns an array structure of SRAM (static random access memory).
2. Description of the Related Art
In recent years, a semiconductor memory device is designed to increase a capacity and an operating speed in accordance with advancement of the micro-fabrication technology and a demand for improved system throughput. Particularly, there is a demand for SRAM built in a microprocessor to accelerate the cycle time and incorporate the multi-bit architecture along with improvement of the microprocessor's operating frequency and an increasing data bit width.
FIG. 6
exemplifies a conventional SRAM configuration (first conventional example). The SRAM uses a memory cell array
101
to arrange a plurality of memory cells
102
as storage elements in an array. The memory cell array
101
is provided with a plurality of word lines WL in a row direction and a plurality of pairs of bit lines BL and /BL in a column direction. Each memory cell
102
contains a pair of storage nodes (not shown) which are complementary to each other. The storage nodes are connected to each pair of bit lines BL and /BL via a switching circuit (not shown) which is connected to each word line WL. Each pair of bit lines BL and /BL is connected to a plurality of read/write circuits
103
. Each word line WL is commonly connected to an address decoder
104
.
An address signal is input to the SRAM. The address decoder
104
selects one of word lines WL. The selected word line WL is connected to a plurality of memory cells
102
. The corresponding read/write circuits
103
each read or write data to the memory cells
102
via each pair of bit lines BL and /BL.
In this SRAM, each pair of bit lines BL and /DL is connected to many memory cells
102
. Each pair of bit lines BL and /BL greatly increases a capacity load owing to capacities of a terminal and wiring connected to the storage node for each memory cell
102
. From t he viewpoint of space saving, however, each memory cell
102
uses a small transistor consuming a little driving force. Normally, the switching circuit in each memory cell
102
comprises pass transistors based on N-type MOSFETS. Accordingly, each memory cell
102
transmits just a slight signal to each pair of bit lines BL and /BL.
Further, the read/write circuits
103
each are provided with a sense amplifier for amplifying a slight amplitude difference between each pair of bit lines BL and /BL. During a read operation, an electric potential level for a pair of bit lines BL and /BL is set (precharged) to the H level. A change in the electric potential level causes a read of data stored in each memory cell
102
. During a write operation, the electric potential level (H level) for one of a pair of bit lines BL and /BL changes to the ground level (L level) according to the write data. A difference between the electric potential levels causes data to be written to each memory cell
102
.
When a pair of bit lines BL and /BL is subject to a large capacity load, the thus configured SRAM needs to charge and discharge these bit lines within a clock cycle. There may be the case where write and read operations alternate successively. When the pair of bit lines BL and /BL changes to the L level during a write operation, it must be precharged completely until the next read operation starts. Since the read operation is a slight amplitude operation, an incomplete precharge causes malfunction. Namely, if the electric potential for a pair of bit lines BL and /BL does not reach the specified H level completely, an offset occurs on the pair of bit lines BL and /BL during a read operation, causing malfunction. The SRAM's operating frequency depends on the time for charging and discharging a pair of bit lines BL and /BL.
The thus configured SRAM causes a large capacity load on a pair of bit lines BL and /BL. Consequently, it is impossible to charge and discharge the pair of bit lines BL and /BL in a short time. It has been difficult to improve the operating frequency.
For decreasing the capacity load for a pair of bit lines, it just needs to decrease the number of memory cells connected to each pair of bit lines. If the SRAM should maintain the same storage capacity, the number of a pair of bit lines increases. This also increases circuits other than memory cells, thus increasing the SRAM area.
Hierarchizing a pair of bit lines is a known method for decreasing a capacity load on a pair of bit lines without increasing the SRAM area.
FIG. 7
exemplifies another memory cell array configuration in the conventional SRAM (second conventional example).
In this configuration example, a memory cell array
201
is divided into a plurality of sub-arrays
202
. The bit lines BL and /BL are hierarchized into a plurality of local bit lines
204
and a global bit line
205
. The local bit lines
204
are connected to memory cells
203
in each sub-array
202
. A plurality of local bit lines
204
is commonly connected to the global bit line
205
.
The bit line is a bidirectional signal line. The local bit line
204
and the global bit line
205
are each connected via switching means
206
comprising pass transistors. Each switching means
206
is controlled by an address signal (decode output for sub-array selection) supplied via an address signal line
207
. During a memory access, an address decoder (not shown) selects the memory cell
203
and the sub-array
202
which contains the memory cell
203
. Further, the switching means
206
connects the local bit line
204
in the selected sub-array
202
to the global bit line
205
. In this manner, data is read or written.
According to this configuration, the bit line's capacity load increases for the size of the sub-array
202
. However, the terminal capacity for the memory cell
203
decreases to a reciprocal of the number of sub-arrays
202
. Consequently, the total capacity load decreases, increasing the SRAM operating frequency.
However, this configuration requires four bit lines per memory cell
203
. The size of each memory cell
203
is approximately four times as large as the wiring pitch. One of the four bit lines functions as a power supply line. In order to implement the SRAM in this example, the bit line requires two types of wiring layers. Though the capacity load on the bit line is reduced, a precharge to the global bit line
205
must be sufficiently performed after the write operation when write and read operations alternate successively. There has been the problem of restricting the operating frequency.
FIG. 8
exemplifies yet another memory cell array configuration in the conventional SRAM (third conventional example). The configuration example provides the global bit line for writing and reading in the memory cell array having the configuration as shown in FIG.
7
.
In each sub-array
202
of memory cell array
201
′, one of local bit lines
204
is connected to a buffer circuit
210
. Each buffer circuit
210
is commonly connected to a reading global bit line
212
which connects with a read circuit
211
. The memory cell array
201
′ is configured to be a so-called single-end type in which the reading global bit line
212
is driven during a read operation. This configuration can decrease the number of bit lines.
Read and write operations can be performed independently by dividing the global bit line into the read function (
212
) and the write function (
205
). In this case, write and read operations coexist only on the local bit line
204
. The precharge after write operation affects the operating frequency only on the local bit line
204
subject to a small capacity load. Further, a read operation uses a CMOS-level signal. Pr

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