Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-01-23
2003-10-07
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090, C324S1540PB
Reexamination Certificate
active
06630838
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuits, and more specifically to programmable logic devices.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a class of integrated circuits (ICs) that can be programmed by a user to emulate various logic functions. Logic designers typically use PLDs to implement control logic in electronic systems because they are relatively easy to program, and often can be reprogrammed to update the emulated logic function. This often makes the use of PLDs less costly in comparison to custom hardwired or “application specific” integrated circuits (ASICs).
Like many integrated circuits, PLD manufacturers test their PLDs to avoid selling defective devices to customers. Part of this testing may include a burn-in test procedure that involves placing the PLDs on load boards that apply test signals to the PLDs while they are heated in an oven.
FIGS. 1 through 3
are simplified diagrams depicting a burn-in oven
1
during a conventional static burn-in test. Load boards
10
are mounted in oven
1
with each load board
10
having several PLDs
100
mounted thereon. Load boards
10
apply test signals to the input/output (I/O) terminals of PLDs
100
. For example, as indicated in
FIG. 2
, each PLD
100
is mounted on a test fixture
12
that is connected to a pair of signal conduits
14
and
16
(e.g., power and ground) formed in load board
10
. Referring to
FIG. 3
, each I/O terminal (e.g., solder bump)
110
of PLDs
100
contacts either a power mount
12
-
1
or a ground mount
12
-
2
, which are respectively connected to power signal conduit
14
and ground signal conduit
16
. During the burn-in testing procedure, PLDs
100
are periodically removed from oven
1
and tested for operability. Any PLDs that fail the burn-in testing are discarded.
A typical cause of PLD failure during burn-in testing is the heat-induced migration of the various dopants that form the conductive channels in the PLD substrate. Dopants (e.g., boron or phosphorous) are introduced during fabrication to produce conductive channels and other doped regions that are separated by un-doped regions of the substrate. During burn-in testing, the heated oven increases the tendency of these dopants to migrate into the un-doped regions of the substrate. If sufficient migration takes place, adjacent regions become shorted to each other, thereby causing the PLD to fail.
Although static burn-in testing tends to detect many defective PLDs, some PLDs that pass static burn-in testing may fail under actual operating conditions. That is, after a customer receives a PLD, the PLD is typically programmed (configured) to implement a desired logic function. During subsequent operation, the various transistors of the PLD are dynamically operated (i.e., repeatedly turned on and off) during the implementation of the logic function. As is understood in the art, this dynamic operation stresses the doped regions of the PLD by repeatedly altering the voltages applied to these regions. This increased stress increases the tendency for dopants to migrate, thereby increasing the chance that “weak” devices will fail if operated under normal operating conditions after an extended period of time. Therefore, because static burn-in testing maintains the various configurable parts of the PLD in a static (unchanging) state, it is not optimal for detecting some defective PLDs that, if shipped to a customer, may potentially cause the customer to stop using the PLD manufacturer's products.
Conventional methods for providing dynamic burn-in testing are complex and expensive. First, each PLD must be programmed to implement a test logic operation that operates in response to applied dynamic test signals. Second, the transmission of the dynamic test signals to the PLDs during burn-in testing requires more than the two conduits that are used in static burn-in testing (i.e., power conduit
14
and ground conduit
16
; see FIG.
2
). For example, a clock signal and/or other dynamic test signals must be provided to appropriate terminals of each PLD under test. Because each burn-in load board can hold dozens of devices, a large number of conduits may be required on each load board to support conventional dynamic burn-in testing, thereby greatly increasing the cost of each load board. Finally, a modified burn-in oven must be provided that facilitates passage of the test signals to the load boards.
What is needed is a practical dynamic burn-in testing procedure that eliminates the extra costs associated with conventional dynamic burn-in test methods, discussed above.
SUMMARY OF THE INVENTION
The present invention is directed to a method for dynamically burn-in testing a PLD by either configuring or fabricating the PLD to implement a self-executing logic operation that automatically and repeatedly turns on and off selected transistors of the PLD using only static test signals. The PLD is placed on a conventional load board and heated in a conventional oven while static test signals are applied to selected terminals of the PLD through the load board, thereby performing a dynamic burn-in test due to the PLD's implementation of the self-executing logic operation. Accordingly, dynamic burn-in testing is performed using conventional static burn-in testing equipment (i.e., without the need for externally supplied dynamic test signals), thereby minimizing PLD testing costs.
In accordance with an embodiment of the present invention, the self-executing logic operation implemented by the PLD during dynamic burn-in testing includes a driving logic function and a driven logic function. The driving logic function, which is implemented in a first portion of the PLD logic resources, generates an internal dynamic test signal in response to externally-supplied static test signals, thereby avoiding the need for externally supplied dynamic signals. The internal dynamic test signal is then supplied to the driven logic function, which is implemented in a second portion of the PLD logic resources. Specifically, the second portion of the PLD logic resources is configured to repeatedly perform a logic operation such that selected transistors are continuously turned on and off in response to the internal dynamic test signal.
In accordance with a disclosed embodiment of the present invention, the driving logic function of the self-executing logic operation is implemented as an oscillator formed by connecting two logic elements (e.g., an AND gate and an inverter) in a loop such that the logic elements generate the internal dynamic test signal that alternates between logic “0” and logic “1”. The alternating internal dynamic test signal is tapped from one of the logic elements and is supplied to the driven logic function of the self-executing logic operation. An optional delay circuit is provided between the logic elements to increase the test signal period (i.e., the period between sequential logic “0” and logic “1” signals) to a suitable level. By implementing an oscillator in this manner, the present invention avoids the need for an external clock signal, thereby facilitating dynamic burn-in testing using static test signals.
In the disclosed embodiment, the driven logic function of the self-executing logic operation includes a 16-bit counter that repeatedly cycles through its count cycle in response to the internal dynamic test signal, which is utilized as a clock signal. Accordingly, the transistors implementing the 16-bit counter are repeatedly turned on and off. By configuring the logic resources of the PLD to implement a 16-bit counter (or another self-executing and repeating logic function), the need for externally-supplied dynamic test signals is removed, thereby further facilitating dynamic burn-in testing using static test signals.
Further, in accordance with the disclosed embodiment, one or more I/O resources are configured to selectively apply count values generated by the 16-bit counter to associated I/O terminals of the PLD. During burn-in testing, a first static test signal is utiliz
Behiel Arthur J.
Bever Patrick T.
Cuneo Kamand
Hollington Jermele
Xilinx , Inc.
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