Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-02-13
2003-02-11
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S118000
Reexamination Certificate
active
06518910
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal processing circuit, and more particularly to a signal processing circuit having an analog/digital conversion function for converting a signal from a signal source such as a photoelectric conversion unit into a digital signal.
2. Related Background Art
An amplification type image sensor is being studied and developed, in which photoelectrically excited carriers are amplified by active elements in a pixel unit. Such a photoelectric conversion device generally called a CMOS image sensor and various circuits such as logical circuits can be integrated on the same chip. Integration of an image sensor and an A/D converter and other circuits has been studied to date.
Integration of an image sensor and an A/D converter includes, for example, one A/D converter provided for each pixel, one A/D converter provided for each column, one A/D converter provided for the sensor output unit, or the like. Integration of one A/D converter for each column has been studied most vigorously.
The fundamental technology of a conventional A/D converter will be described with reference to FIG.
1
. In the following, an A/D converter of the type that only one comparator is used and a conversion result is obtained while changing a reference voltage, will be described illustratively without using a relatively large scale parallel type such as a flash type and a two-step type.
An A/D converter is basically constituted of one comparator and one reference voltage generator.
A comparator
11
has a non-inverting input terminal
12
and an inverting input terminal
13
. If an input to the non-inverting input terminal
12
is larger than an input to the inverting input terminal
13
, a logical high level (usually a power source voltage) is output from a comparator output terminal
14
, whereas if it is smaller, a logical low level (usually a GND level) is output.
In order to realize an A/D converter by using the comparator, a comparison reference voltage
15
is input to the inverting input terminal and a voltage
16
to be A/D converted is input to the non-inverting input terminal.
A comparison reference voltage generator unit outputs a ramp voltage which is synchronous with a digital counter and monotonously increases its amplitude, i.e., a derivative of the voltage with respect to time is always positive during each A/D conversion operation. A digital value is obtained from a count of the counter when an output of the comparator
11
is inverted.
In the case of a sequential comparison type, in accordance with an A/D conversion result obtained sequentially from the upper bit, the next reference voltage is determined and this operation is repeated.
If an output voltage from a photoelectric conversion element (e.g., a photodiode) is input to the non-inverting input terminal, the A/D converter converts input light into a digital signal.
The terms “inverting” and “non-inverting” are named after the output logic. There is no strict discrimination therebetween if only the transition of the output from the low level to the high level or vice versa is taken into consideration. In the following description, even if inverting is replaced by non-inverting, there is no practical problem. In this case, the logic of an encoder at the back stage may be changed or a protocol for processing the result after A/D conversion may be is changed.
Next, with reference to
FIG. 2
, the fundamental technology of an A/D converter used by a CMOS image sensor having one A/D converter per one column (hereinafter called a column A/D type CMOS sensor) will be described.
In an active pixel type sensor such as a CMOS sensor, generally a plurality of voltage sources, i.e., pixels, are connected in parallel to one common column
21
. The amount of optically induced current of each pixel is too small and the generated voltage is insufficient for driving the column. To solve this, generally, an impedance conversion amplifier called a source follower is provided to supply its output to the column. The photoelectric conversion results of respective pixels are equivalently considered as voltage sources
22
,
23
and
24
. An output of each voltage source is selected by a corresponding one of select switches
25
,
26
and
27
and supplied to the column to enable selective data read. Reference numeral
28
represents a constant current source for the source followers.
In the column A/D type CMOS sensor, a voltage selectively read in the above manner is supplied to a compartor
29
at which the voltage is compared with a reference voltage
30
to attain conversion.
The column A/D type CMOS operating on the basis of the above-described principle is associated with the following problems.
A first problem is concerned about consumption current. If an A/D converter is not provided for each column, the current consumed at each column is only current
28
for the source followers. In a column A/D type CMOS sensor, consumption current of the comparator (generally constituted mainly of a differential amplifier)
29
is required in addition to the consumption current by the source followers. A general image sensor has several hundred to several thousand columns. The total consumption power is therefore several hundred to several thousand times the consumption power of one column, and an increase in the consumption power cannot be neglected.
A second problem is concerned about a variation in gains of A/D converters. There is a variation in the conversion characteristics of A/D converters provided for columns. This variation appears as a differential non-linear error and an integration non-linear error which are caused by an offset voltage variation in initial stage differential amplifiers in A/D converters and a variation in performances of reference voltage generators, and the like. If the characteristics of A/D converters of respective columns are different, vertical fogged stripes are formed in an image and the image quality is degraded.
A third problem is concerned about a variation in input-output characteristics, particularly, amplification factors, of source followers. There is a general tendency that the gate length and width of a MOS transistor are shortened and narrowed in order to increase the integration degree. An image sensor has also this tendency. At such a high integration degree, there a variation in gains of source followers to be caused by variations of mutual conductances gm and differential source/drain resistances rds generated by a variation in manufacture processes. A variation in gains is several % at the most and a picked-up image is fogged.
FIG. 3
shows the structures of a conventional MOS type solid state image pickup device and an A/D converter for A/D converting an analog voltage signal of the image pickup device, and
FIG. 4
is a timing chart illustrating the operation. A unit cell is constituted of a photodiode
81
, an amplifying transistor
82
, a select transistor
83
and a reset transistor
84
.
A signal accumulated in a photodiode
81
(
81
-
1
-
1
,
81
-
1
-
2
, . . . ) of each cell is amplified by an amplifying transistor
82
(
82
-
1
-
1
,
82
-
1
-
2
, . . . ) and read out to a vertical signal line or detection node
88
(
88
-
1
,
88
-
2
, . . . ) in the form of voltage. Since the amplifying transistor
82
and a load transistor
89
(
89
-
1
,
89
-
2
, . . . ) form a source follower, a voltage corresponding to the signal in the photodiode
81
is read out to the vertical signal line
88
. The MOS type solid image pickup device constructed as above is associated with a problem of fixed pattern noises corresponding to a variation in threshold voltages of amplifying transistors
82
. Therefore, a noise canceling circuit is generally used, the operation of which will be described in the following.
By applying a pulse
501
to a select signal line
86
-
1
, the row of the amplifying transistors
82
-
1
-
1
,
82
-
1
-
2
, . . . is activated. At this time, output signal voltages corresponding to the signals accumulated in t
Hashimoto Seiji
Sakuragi Takamasa
Yamashita Yuichiro
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Wamsley Patrick
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