Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1997-12-31
2003-10-07
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06631393
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of computer arithmetic and more particularly to the field of binary addition.
BACKGROUND OF THE INVENTION
Two of the most critical factors in determining the performance of a computer system are the internal clock frequency and the datapath width of the processor. A far more powerful computer system can be built with a 200 MHz, 32 bit processor than with a 8 MHz, 8 bit processor. However, there is an inherent conflict between these two factors in a key component of a processor, a binary adder. The conflict results from the dependence of the latency on the width of a typical binary adder. For example, the latency of a parallel ripple adder depends on the operand width because sufficient time must be allowed for a carry bit to propagate through one adder stage for every bit of the operand width. The latency can be reduced by using a carry lookahead technique wherein the carry bits into every stage can be calculated simultaneously by expressing every carry bit as a function of all of the preceding, simultaneously available operand bits. However, the carry lookahead technique is limited by the fan-in restrictions of the circuit technology, in that additional levels of logic are needed as the number of inputs to the highest order stage increases. These additional levels increase the latency, so again, the latency depends on the operand width. In response to this dependence of adder latency on adder width, a novel approach to binary addition has been developed.
SUMMARY OF THE INVENTION
An adder for calculating an N bit sum from an N bit augend and an N bit addend is disclosed. The adder comprises a first circuit for speculatively calculating bit N−1 of the sum based only on bit N−1 of the augend, bit N−1 of the addend, and a limited carry bit. The adder also comprises a second circuit for calculating the limited carry bit based only on K bits of the augend and K bits of the addend, where K is less than N−1. The adder also comprises a third circuit for detecting a potential difference between the limited carry bit and an unlimited carry bit.
REFERENCES:
patent: 4761760 (1988-08-01), Tomoji
patent: 5483478 (1996-01-01), Chiang
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Ngo Chuong Dinh
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