Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Magnetic saturation
Reexamination Certificate
2001-05-31
2003-11-18
Patel, Rajnikant B. (Department: 2838)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Magnetic saturation
C324S763010, C361S056000
Reexamination Certificate
active
06650103
ABSTRACT:
FIELD OF INVENTION
This invention relates to a magnetic snapback sensor circuit, and to such a magnetic snapback sensor circuit useful in an electrostatic discharge (ESD) circuit.
BACKGROUND OF INVENTION
Snapback circuits employ the inherent parasitic bipolar transistor associated with each MOS transistor to accommodate increased current flow through such bipolar transistor to lower the maximum voltage at the MOS drain electrode in response to an electrostatic discharge. The original publication describing the snapback operation is “Snap-Back; A Stable Regenerative Breakdown Mode of MOS Devices,” A. Ochoa, Jr., F. W. Sexton, T. F. Wrobel, G. L. Hash and R. J. Sokel, IEEE Transactions on Nuclear Science, Vol. NS-30, No. 6, pp. 4127-4130, December 1983. Electrostatic discharge generated by, for example, a person walking on a rug can introduce transient high voltage current flow of up to 2-3 amps for up to 150 nanoseconds, enough to damage or destroy integrated circuit components. One shortcoming to such snapback circuit solutions was that during the snapback mode the voltage applied to a circuit node by the ESD pulse could rise high enough to damage some on-circuit components (the snapback event was pronounced). To avoid this, techniques were employed to reduce the snapback effect such as bias the gate of the MOS transistor with respect to its drain to turn on the MOS transistor; this reduced the snapback effect and the associated voltage. One example of this is described in U.S. Pat. No. 5,940,258.
One problem with this approach is that during the high current exposure of the MOS transistor during the ESD event, the transistor gate oxide and oxide-silicon interface can be damaged by hot electrons emanated from the adjacent avalanching drain to backgate junction diode. To solve this problem, a timer circuit was employed to allow the MOS transistor to be biased on only for a limited amount of time. See U.S. Pat. No. 5,835,146.
A problem with the timer circuit approach above is that for low voltage ESD events, the time between timer activation and the ESD-induced activation voltage reaching a high enough threshold causes the timer to shut off (lower the voltage) on the MOS gate, which reintroduces the snapback high voltage the transistor is meant to shut off. In addition the timer would only attempt to shutoff the MOS gate once. Thus if the voltage took too long to reach a predetermined trigger level the timer would not operate as intended.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an improved magnetic snapback sensor circuit and method and to an improved electrostatic discharge circuit employing such a magnetic snapback sensor circuit and method.
It is a further object of this invention to provide such an improved magnetic snapback sensor circuit and method and electrostatic discharge circuit which responds even to low voltage, low rise transients.
It is a further object of this invention to provide magnetic snapback sensor circuit and method and electrostatic discharge circuit which introduces no additional resistive load.
It is a further object of this invention to provide magnetic snapback sensor circuit and method and electrostatic discharge circuit which is achievable with existing MOS components without re-engineering of the snapback MOS transistor.
It is a further object of this invention to provide magnetic snapback sensor circuit and electrostatic discharge circuit which does not operate under normally functional IC operating conditions.
It is a further object of this invention to provide magnetic snapback sensor circuit and method and electrostatic discharge circuit which is implementable with PMOS as well as NMOS transistors, and can be disposed between the power supply and I/O as well as between power supply terminals.
The invention results from the realization that a truly improved, simpler snapback sensor circuit can be achieved by using a conductor carrying current from a snapback circuit to magnetically induce a current in a conductor loop and detecting the induced current to operate the gate of the MOS transistor in the snapback circuit and more specifically to operate such an MOS transistor in an electrostatic discharge circuit either directly or through a timer or other control circuit.
This invention features a magnetic snapback sensor circuit for sensing current transients imposed on a snapback circuit. There is a current conductor loop and a conductor carrying current from the snapback circuit subject to current transients and intersecting with the conductor loop for magnetically generating a current in the loop. A current detector circuit generates an output responsive to the current flowing in the loop induced by a current transient.
In the preferred embodiment the loop may include a single turn, the current detector may include a Hall effect circuit, the Hall effect circuit may include a magnetotransistor circuit.
This invention also features an electrostatic discharge circuit including a snapback circuit including an MOS transistor with an inherent parasitic bipolar transistor and a magnetic snapback sensor circuit in series with the snapback circuit. The magnetic snapback sensor circuit includes a conductor loop, a conductor carrying current from a snapback circuit subject to electrostatic discharge and intersecting with the conductor loop for magnetically generating a current in the loop. There is a current detector circuit for generating an output responsive to the current flowing in the loop induced by an electrostatic discharge for controlling the operating bias on the gate of the MOS transistor.
In a preferred embodiment the MOS transistor may be an NMOS type. The magnetic snapback sensor circuit may include a timer circuit responsive to the output for timing the application of a bias to the gate. There may be a comparator circuit responsive to the output. The snapback circuit and a magnetic snapback sensor circuit may be disposed on an integrated circuit chip. The integrated circuit chip may include additional integrated circuitry powered by the same power supply. The loop may include a single turn. The current detector may include a Hall effect circuit and the Hall effect circuit may be implemented with a magnetotransistor transistor circuit. The snapback circuit and the magnetic snapback sensor circuit may be in series between power supply terminals or between a power supply terminal and an I/O terminal.
REFERENCES:
patent: 4823075 (1989-04-01), Alley
patent: 5570034 (1996-10-01), Needham et al.
patent: 5744842 (1998-04-01), Ker
patent: 5835146 (1998-11-01), Stone
patent: 5940258 (1999-08-01), Duvvury
patent: 6373104 (2002-04-01), Smith
Analog Devices Inc.
Iandiorio & Teska
Patel Rajnikant B.
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