Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-09-25
2003-02-11
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S780000, C438S783000, C438S949000, C148SDIG001
Reexamination Certificate
active
06518196
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and especially to a method of forming resist holes using lithography techniques.
2. Description of the Background Art
As semiconductor device dimensions have been more and more decreasing in recent years, in terms of control of resist hole dimensions by lithography techniques, it is getting increasingly difficult to form resist holes of the same diameter (the resist hole diameter is hereinafter referred to as a “hole diameter”). The resist hole is a hole formed in a resist, the resist being a masking material in formation of a contact hole in an interlayer film on a semiconductor substrate, for example. It is hereinafter simply referred to as a “hole”.
In formation of holes in a resist by a projection aligner, the hole diameter may have pitch dependence depending on lighting conditions of the projection aligner. The pitch dependence represents a characteristic that when a resist has a plurality of holes, the hole diameter varies depending on the center-to-center distance of adjacent holes (hereinafter referred to as a “hole pitch”).
Now, the pitch dependence will be set forth in more detail.
FIGS. 49 and 50
are graphs of the relationship between the hole pitch and the hole diameter in conventional techniques, the graphs illustrating simulation results in consideration of only an optical system in a projection aligner. A laser used in the simulations is a KrF excimer laser operating at wavelengths of 248 nm, and the dimensions of holes in a masking material for use in formation of holes in a resist are 0.22 &mgr;m. A desired design value for the hole diameter is 0.16 &mgr;m.
FIG. 49
is a graph for a constant NA (NA=0.6) and &sgr;=0.6, 0.7, and 0.8; and
FIG. 50
is a graph for a constant &sgr; (&sgr;=0.6) and NA=0.6, 0.65, and 0.7. NA is the numerical aperture of a lens between a resist formed on the semiconductor substrate, and a masking material for use in formation of holes in a resist. NA represents the resolution of the lens. &sgr; is a constant given by
&sgr;=
iNA/NA
(1)
where iNA is the numerical aperture for light incident on the masking material.
As shown in
FIG. 49
, under the lighting conditions of NA=0.6 and &sgr;=0.6, the hole diameter, when the hole pitch is between 0.4 and 0.5 &mgr;m, is mostly smaller than the desired design value of 0.16 &mgr;m, and as the hole pitch increases, the hole diameter mostly increases. For the hole pitch between 0.5 and 1.0 &mgr;m, the hole diameter is nearly equal to the desired design value of 0.16 &mgr;m. Under the lighting conditions of NA=0.6 and &sgr;=0.7, the hole diameter, when the hole pitch is between 0.4 and 0.5 &mgr;m, is slightly larger than the desired design value of 0.16 &mgr;m, but as a whole, it is nearly equal to the desired design value of 0.16 &mgr;m. Under the lighting conditions of NA=0.6 and &sgr;=0.8, the hole diameter, when the hole pitch is between 0.4 and 0.6 &mgr;m, is larger than the desired design value of 0.16 &mgr;m, and as the hole pitch increases, the hole diameter mostly decreases. For the hole pitch between 0.6 and 1.0 &mgr;m, the hole diameter is nearly equal to the desired design value of 0.16 &mgr;m.
On the other hand, as shown in
FIG. 50
, under the lighting conditions of NA=0.6 and &sgr;=0.6, the hole diameter, when the hole pitch is between 0.4 and 0.5 &mgr;m, is mostly smaller than the desired design value of 0.16 &mgr;m and as the hole pitch increases, the hole diameter mostly increases. For the hole pitch between 0.5 and 1.0 &mgr;m, the hole diameter is nearly equal to the desired design value of 0.16 &mgr;m. Under the lighting conditions of NA=0.65 and &sgr;=0.6, the hole diameter, when the hole pitch between 0.4 and 0.5 &mgr;m, is slightly smaller than the desired design value of 0.16 &mgr;m, but as a whole, it is nearly equal to the desired design value of 0.16 &mgr;m. Under the lighting conditions of NA=0.7 and &sgr;=0.6, the hole diameter is nearly equal to the desired design value, 0.16 &mgr;m.
As above described, under some lighting conditions (the values NA and &sgr;) of the projection aligner and for the hole pitch between 0.4 and 0.5 &mgr;m or between 0.4 and 0.6 &mgr;m, the hole diameter has a characteristic of depending on the hole pitch. The aforementioned “pitch dependence” refers to this characteristic.
As shown in
FIGS. 49 and 50
, the pitch dependence of the hole diameter can be virtually eliminated by the settings of NA=0.6 and &sgr;=0.7 or the settings of NA=0.7 and &sgr;=0.6. The values NA and &sgr;, however, exercise influence on the resolution and focal depth of a lens for focusing light on the resist and therefore, they cannot be determined for only the purpose of eliminating the pitch dependence. Besides, the values NA and &sgr; may sometimes be fixed by the specifications of the projection aligner, in which case they cannot be determined freely on the manufacturing end of the semiconductor device. That is, the hole diameters of holes formed in a resist may have pitch dependence depending on the required resolution and focal depth and depending on the projection aligner to be used.
Let the lighting conditions be NA=0.6 and &sgr;=0.8 based on the required resolution and focal depth and on a projection aligner to be used. At this time, as shown in
FIG. 49
, the hole diameter, when the hole pitch is between 0.4 and 0.6 &mgr;m, mostly decreases with increasing hole pitch. Use of a projection aligner with a small &sgr; for reduction of such pitch dependence creates a problem of reducing the resolution of a lens. Use of a projection aligner with a large NA for reduction of the pitch dependence creates a problem of reducing the focal depth of a lens; in addition, such a projection aligner with a large NA is expensive and therefore, reducing the pitch dependence through the use of such a projection aligner becomes a cause of increasing the semiconductor device manufacturing cost. While in the above description, the lighting conditions of NA=0.6 and &sgr;=0.8 are presented as conditions for developing the pitch dependence which represents the characteristic that the hole diameter decreases with increasing hole pitch, the hole diameter also varies according to the type of a resist to be used and to the diameters of holes in a masking material for use in formation of holes in a resist. Therefore, not only the lighting conditions of NA=0.6 and &sgr;=0.8 but also various other conditions develop the above pitch dependence.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a method of manufacturing a semiconductor device, comprising the steps of: (a) forming a resist on an object to be etched; (b) forming in the resist a plurality of holes a pitch of which includes different pitches; and (c) performing ion implantation on the resist to reduce pitch dependence caused to diameters of the holes.
According to a second aspect of the present invention, the method of manufacturing a semiconductor device of the first aspect further comprises the step of: (d) between the steps (b) and (c), performing processing for reduction of the diameters of the holes.
A third aspect of the present invention is directed to a method of manufacturing a semiconductor device, comprising the steps of: (a) forming a resist on an object to be etched; and (b) forming a plurality of holes in the resist, wherein the holes include a first hole of a first pitch and a second hole of a second pitch larger than the first pitch. The method further comprises the step of: (c) performing ion implantation on the resist to make the amount of increase in the diameter of the second hole larger than that in the diameter of the first hole.
A fourth aspect of the present invention is directed to a method of manufacturing a semiconductor device, comprising th
Tsujita Kouichirou
Yamada Tetsuya
Yamaguchi Atsumi
Dang Trung
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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