Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-08-14
2003-10-07
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S143000, C341S200000, C341S068000, C341S069000
Reexamination Certificate
active
06630898
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to quantization circuits. More particularly, the present invention relates to an apparatus and method that uses a feed-forward auto-zero technique, and a positive feedback arrangement to increase the signal to acceptable logic levels. Switched capacitor techniques are used to adjust the common-mode voltage for reduced power-supply voltage requirements.
BACKGROUND OF THE INVENTION
A one-bit over-sampling analog-to-digital converter (
600
) is depicted in FIG.
6
. This type of analog-to-digital converter (ADC) is often referred to as a first order delta-signal (&Dgr;&Sgr;) modulator. As shown in the figure, the first order &Dgr;&Sgr;-modulator (
600
) includes a summer (
601
), an integrator (
602
), a 1-bit ADC (
603
) a digital low pass filter (
604
), and a 1-bit digital-to-analog converter (
605
). The first order &Dgr;&Sgr;-modulator (
600
) receives an analog signal and produces an N-bit digital code output.
In operation, an analog signal and an output of 1-bit digital-to-analog converter (DAC)
605
are fed into summer
601
. The summer (
601
) provides an output that corresponds to the difference between the analog input signal and the output of DAC
605
. The integrator (
602
) provides an integration signal in response the difference signal. The 1-bit ADC (
603
) produces a digital bit by converting by comparing the integration signal to a predetermined threshold level (i.e., mid-supply level). This digital bit is fed into the 1-bit DAC, which produces an analog voltage that corresponds to one of two voltages (i.e., +VREF and −VREF). Digital low pass filter (LPF)
604
receives the digital bit from the 1-bit ADC (
603
) and produces an N-bit digital code output.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for an auto-zeroed quantizer that has a unit delay characteristic. Switched capacitor techniques are employed to adjust the input common-mode voltage to a proper common-mode voltage for the quantizer. A feed-forward auto-zero scheme is used to initialize the apparatus during an initialization phase. After the initialization phase, a differential input signal is amplified to provide a differential amplified signal. A positive feedback circuit is subsequently activated to increase the difference in the differential amplified signal until the difference saturates at a logic level. The logic level decision is stored in a memory circuit such as a latch. The unit delay quantizer may be utilized in a converter circuit such as a &Dgr;&Sgr; modulator.
According to a first aspect of the invention, an apparatus is directed to provide a quantized differential output signal in response to a differential input signal. The apparatus includes a differential amplifier. The differential amplifier includes a differential input that is coupled to the differential input signal, and a first and second output that are arranged to provide a differential intermediate signal in response to the differential input signal during an amplification phase. The amplification phase is activated after an initialization phase is complete. An auto-zero circuit is coupled to the first and second output of the differential amplifier. The auto-zero circuit is arranged to initialize the differential intermediate signal during an initialization phase. The differential intermediate signal is substantially zero differentially after the initialization phase is complete. A positive gain circuit is coupled to the differential output of the differential amplifier. The positive gain circuit is arranged to increase the gain of the differential intermediate signal during a decision phase such that the differential intermediate signal saturates to a differential logic level. The decision phase is activated after the amplification phase is complete. The quantized differential output signal is associated with the differential intermediate signal at the end of the decision phase.
According to a second aspect of the invention, an apparatus is directed to quantizing a differential input signal. The apparatus includes a means for adjusting. The means for adjusting is arranged to receive the differential input signal and provide a first intermediary differential signal that corresponds to the differential input signal with an adjusted common-mode voltage. A means for amplifying is arranged to receive the first intermediary differential signal and provide a second intermediary differential signal when the apparatus is in an amplification phase after an initialization phase is complete. The second intermediary differential signal corresponds to the first intermediary differential signal that is increased in amplitude by a gain factor. A means for disabling is arranged to disable the means for amplifying when the apparatus is in the initialization phase. A means for initializing is coupled to the means for amplifying and arranged to initialize the second intermediary differential signal during the initialization phase such that the second intermediary differential signal is substantially zero at the end of the initialization phase. A means for providing positive feedback is coupled to the means for amplifying and arranged to increase the amplitude of the second intermediary differential signal during the decision phase. The increased amplitude corresponds to a logic level. A means for storing is coupled to the increased amplitude second intermediary signal and arranged to store the logic level of the increased amplitude second intermediary signal at the end of the decision phase.
According to a third aspect of the invention, a method is directed to quantizing a differential input signal. The method includes adjusting the common-mode voltage of the differential input signal to provide an intermediary signal. By amplifying the first intermediary signal, an amplified signal is provided during an amplification phase and after an initialization phase. The amplified signal is initialized to a value that corresponds to a zero difference differential signal during the initialization phase. Positive feedback is provided to the amplified signal to provide a decision signal during a decision phase and after the amplification phase. The decision signal is a logic level signal that is associated with the polarity of the amplified signal. The decision signal is latched at the conclusion of the decision phase to provide a quantized signal.
REFERENCES:
patent: 4633223 (1986-12-01), Senderowicz
patent: 4803462 (1989-02-01), Hester et al.
patent: 5030954 (1991-07-01), Ribner
patent: 5572107 (1996-11-01), Koch et al.
patent: 5729232 (1998-03-01), Fujimori
patent: 5894284 (1999-04-01), Garrity et al.
patent: 6091300 (2000-07-01), Setty et al.
patent: 6242974 (2001-06-01), Kunst
Hertzberg Brett A.
Jeanglaude Jean Bruner
Merchant & Gould
National Semiconductor Corporation
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