Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated...
Reexamination Certificate
2003-02-03
2003-11-04
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
C257S909000
Reexamination Certificate
active
06642598
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having shallow trench element isolation (referred to as STI hereinafter) regions, obtained by forming shallow trenches in a semiconductor substrate and filling them in with an insulating material, or a multilayer wiring structure.
2. Description of the Prior Art
Accompanying the progress in refinement and high integration of semiconductor devices, refinement of the area of the element isolation region for electrically isolating each circuit element has also been advanced along with a refinement of each circuit element itself mounted on the semiconductor device. In particular, as an element isolation method replacing the LOCOS method that is embracing such a problem as the bird's beak, the STI technique which does not produce transition regions such as the bird's beak in the boundary of an active region and the element isolation region, and is also excellent in flattening the substrate surface, has been adopted widely in recent years. However, it has been revealed that even the STI technique is infested by such problems as will be described below.
Namely, in forming an STI region for isolating the active region it is necessary to flatten the substrate surface, and for that purpose, the chemical mechanical polishing (referred to as CMP hereinafter) technique that has a superior capability for flattening microscopic regions has mainly been employed. More specifically, the STI region is obtained, for example, by forming isolation trenches on the semiconductor substrate, filling in the isolation trenches with an insulating material by depositing the insulating material on the entire surface of the semiconductor substrate, and then flattening the surface of the semiconductor substrate by polishing the insulating material deposited on the regions other than the isolation trenches, that is, the protrusion regions of the semiconductor substrate.
However, it has been known that the STI technique possesses also an essential problem of the dependence of the etching rate of the insulating material being the object of polishing on the density of the underlying pattern. That is, it has a polishing characteristic that the etching rate is low when the protrusion region has a high density, and the etching rate is high when it has a low density. Accordingly, when regions with different pattern densities exist mingled together, the flatness of the surface after CMP exhibits dispersion due to the difference in the etching rate caused by the variation in the density of the pattern.
In order to resolve the dispersion problem in the flatness of the surface after CMP due to the difference in the etching rate caused by the variation in the density of the pattern, various kinds of proposals have been presented in the past.
For example, in Japanese Patent Applications Laid Open, No. 2000-114258 (referred to as disclosed example 1 hereinafter), there is proposed a semiconductor device in which when there exists a variation in the distribution of the protrusion regions necessary for the circuit operation arranged in the semiconductor device, first dummy protrusions with a fixed shape useless for the circuit operation are arranged periodically in regions with sparse distribution of the protrusions, and second dummy protrusions with arbitrary shapes useless for the circuit operation are arranged in regions where the disposition of the first dummy protrusions does not suffice to compensate for the variation in the density.
FIG. 7
illustrates layout of the semiconductor device disclosed in the disclosed example 1. On a silicon substrate
611
, a plurality of protrusions
612
, identified by hatching, necessary for the circuit operation are arranged as a circuit pattern. The manner in which the protrusions
612
appear indicates a distribution that has a variation in the density. In this example, for the region where the arrangement density of the protrusions
612
is sparse, first dummy protrusions
613
useless for the circuit operation are arranged together with the protrusions
612
. The first dummy protrusions
613
of a rectangular pattern (in
FIG. 7
, it is a square pattern) are arranged periodically. Specifically, as the first dummy protrusions, square patterns with side length of 5 &mgr;m are arranged with an interval of 3 &mgr;m. Moreover, sparse regions that still remain unfilled even by the regular arrangement of the first dummy protrusions
613
, are further supplemented by the arrangement of arbitrarily shaped second dummy protrusions
614
. The second dummy protrusions
614
which are useless for the circuit operation are formed at the same time with the formation of the protrusions
612
and the first dummy protrusions
613
.
Furthermore, Japanese Patent Applications Laid Open No. 2001-176959 (referred to as disclosed example 2 hereinafter) proposes to provide two kinds of large and small dummy patterns in the isolation region in order to obtain a semiconductor device of satisfactory surface flatness by enhancing uniformity of polishing rate when an isolation oxide film is polished by a CMP method.
FIGS. 8A
to
8
C are plan views for illustrating the semiconductor device described in the disclosed example 2. Referring to
FIG. 8
, in the semiconductor device, two kinds of large and small dummy patterns
711
that will serve as dummy active regions are provided in an isolation region
710
of a semiconductor substrate
712
, and large dummy patterns
711
b
are arranged regularly arrayed at positions far from principal patterns
709
, while small dummy patterns
711
a
are arranged in the gaps formed in the periphery of the principal patterns
709
.
In the prior art including the disclosed examples 1 and 2, even after isolation trenches formed in the semiconductor substrate are filled with an insulating material such as an oxide film and then subjected to CMP, suppression of variation in the flatness within the wafer plane or within the chip has still been insufficient.
Moreover, even if the deposition thickness of the insulating material that fills in the isolation trenches is devised so as to have a constant value, there is a problem that the variation in the flatness is increased 0n the contrary when the circuit patterns on the wafer are different.
In spite of these circumstances, effective measures against problems in the above have not been found so far. Because of this, it has been necessary in the CMP process to adjust complicated polishing conditions for each product, which led also to the problem of obstructing the enhancement of the efficiency of manufacturing and stabilization of processes.
BRIEF SUMMARY OF THE INVENTION
Summary of the Invention
In the semiconductor device according to the present invention having a plurality of function macro formation regions on the principal face of a semiconductor substrate, the plurality of function macro formation regions include at least a first function macro formation region in which a first function macro is formed, and a second function macro formation region in which a second function macro different from the first function macro is formed, each function macro formation region has an element formation region in which and element is formed, a plurality of dummy semiconductor regions in which elements are not formed, and isolation trenches, filled with a predetermined insulating material, which mutually isolate the element formation region and the plurality of dummy semiconductor regions, and the dummy semiconductor region in a function macro formation region has mutually identical plane shape and identical area, and the area of a first dummy semiconductor region included in the first function macro formation region and the area of a second dummy semiconductor region included in the second function macro formation region are different.
REFERENCES:
patent: 2000-114258 (2000-04-01), None
patent: 2001-176959 (2001-06-01), None
McGinn & Gibb PLLC
NEC Electronics Corporation
Prenty Mark V.
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