Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-10-05
2003-06-17
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S415000, C257S277000, C438S050000
Reexamination Certificate
active
06580146
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an inductive structure integrated in a semiconductor substrate.
The invention specifically concerns an inductive structure integrated in a semiconductor substrate, comprising at least an conductive element on the substrate.
Particularly, but not exclusively, the invention relates to an inductor that is integrated into a SOI (Silicon On Insulator) technology and the following description is made with reference to this application field with the only aim to simplify its explanation.
2. Description of the Related Art
As it is well known, inductors are the most difficult to form in integrated circuits among all the passive electric devices (resistors, capacitors and inductors). In fact, the integrated realization of the inductors requires areas and volumes rather large on silicon, in order to reach the conventionally used inductance values.
A first solution of the prior art to form inductors having high inductance values is the one of forming some planar coils into the semiconductor substrate. It is possible to reach the desired inductance value by forming a proper number of coils.
A second problem, one that appears during the integration of the inductors is the one of obtaining a high quality factor (Q).
In fact, because of the magnetic field associated with the inductance that is integrated into the substrate, parasitic phenomena occur and cause a decrease of the inductance efficiency.
Particularly, Foucault currents which are generated in the silicon substrate tend to counterbalance the magnetic field generated by the current circulating in the inductance.
A solution useful to decrease the influence of such currents is to increase the substrate resistivity.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention is directed to an inductive structure with a high value of the quality factor, which has structural features such to reduce the parasitic currents induced in the substrate, thereby overcoming the limitations that to now are limiting the inductive structures built according to the prior art.
The insulating structure includes a plurality of trench portions formed in a semiconductor substrate and filled with insulating material; and an inductor formed over the insulating structure. The trench portions each surround a respective one of a plurality of semiconductor islands of the substrate.
The features and the advantages of the structure according to the invention will be apparent from the following description of a preferred embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
REFERENCES:
patent: 5874883 (1999-02-01), Uemura et al.
patent: 6054750 (2000-04-01), Imam et al.
patent: 6093599 (2000-07-01), Lee et al.
patent: 6310387 (2001-10-01), Seefeldt et al.
patent: 410321802 (1998-12-01), None
Crane Sara
Iannucci Robert
Im Junghwa
Jorgenson Lisa K.
SEED IP Law Group PLLC
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