Memory access system for vector data processed or to be processe

Details Memory access system for vector data processed or to be processe Memory access system for vector data processed or to be processe

1992-04-13

1994-01-04

Smith, Jerry

Boots, shoes, and leggings

395200, 395250, 395725, 364736, 36423221, 3642281, 364DIG1, 364DIG2, G06F 1516, G06F 300

Patent

active

052769020

ABSTRACT:
A memory accessing system for vector data processed, or to be processed, by a vector processing apparatus comprising plural vector processing units, each unit performing vector data processing for a corresponding portion of vector data elements, the elements being ordered and the vector data processing being carried out in the order of the elements. The system comprises plural memory access units corresponding to the plural vector processing units, each thereof accessing a predetermined portion of the elements of vector data in a main memory. Each memory access unit includes an address generator which receives information defining, and, based thereon, generates addresses for the respective, predetermined portion of the elements of vector data and a priority controller which receives the thus generated addresses from the respective address generators of the plural memory access units and selects an access to an address, from among the received plural addresses, as allowable based on a predetermined order of the elements of vector data and then outputs a memory access signal including the address for which access is selected as allowable by the priority controller, to the memory. The system operates for both direct and indirect addressing modes and, in the latter, address data for the indirect addressing for the predetermined portion of the vector data elements, when read out from the main storage by a corresponding memory access unit is temporarily stored in a vector register thereof and supplied to the address generators of all of the memory accessing units.

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