System and method to measure closed area defects

Details System and method to measure closed area defects System and method to measure closed area defects

2001-07-23

2003-06-24

Dang, Hung Xuan (Department: 2873)

Optics: measuring and testing

Inspection of flaws or impurities

Surface condition

C356S237200, C356S237400, C356S237300

Reexamination Certificate

active

06583871

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to semiconductor processing, and in particular to a system and method adapted to provide in-situ detection and reduction of closed area defects.
BACKGROUND
In the semiconductor industry there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers. In order to accomplish such high device packing densities, smaller feature sizes and more precise feature shapes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry, such as corners and edges, of various features. Achieving smaller dimensions depends, at least in part, on the ability to accurately reproduce mask features on a wafer. For example, if edges are not developed as edges, or if lines have intrusions or extrusions, then the pattern may not produce the desired electrical conductive and/or insulating properties. Thus, a system and method for detecting when defects have been developed on a wafer is required.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically involves photolithography which may consist of more than a hundred acts, during which hundreds of copies of an integrated circuit may be formed on a single wafer. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the photoresist. The photoresist coated substrate is baked to evaporate any solvent in the photoresist composition and to fix the photoresist coating onto the substrate. The baked coated surface of the substrate is next subjected to selective radiation using a mask; that is, a mask is employed to effect an image-wise exposure to radiation. The mask permits radiation to contact certain areas of the photoresist and prevents radiation from contacting other areas of the photoresist. This selective radiation exposure causes a chemical transformation in the exposed areas of the photoresist coated surface. Types of radiation commonly used in microlithographic processes include visible light, ultraviolet (UV) light and electron beam radiant energy. After selective exposure, the photoresist coated substrate is treated with a developer solution to dissolve and remove either the radiation-exposed or the unexposed areas of the photoresist (depending upon whether a positive photoresist or a negative photoresist is utilized) resulting in a patterned or developed photoresist.
The process may be repeated a number of times depending on the desired number of layers and features to be formed. The layering process creates electrically active regions in and on the semiconductor wafer surface. If the patterns are not substantially accurately reproduced on the wafer surface, then the electrically active regions may not perform as desired, leading to an overall degradation of chip performance. In particular, closed area defects such as malformed or undeveloped edges, corners and lines as well as undesired depressions, dimples, protrusions and pinholes in the layers may adversely affect the performance of the semiconductor. Adverse effects may include increased resistance, decreased capacitance, ineffective insulation between layers and features, and poor conductivity and interconnections between layers and features.
Conventional methods for detection and reduction of closed area defects have been ineffective in mitigating closed area defect problems and associated yield losses and costs for many reasons. For example, conventional methods rely on pre-set timed check points to monitor and detect for the presence of defects on a wafer as opposed to allowing the detection system to operate in a continuous manner on the fabrication line. In addition, conventional methods and systems do not provide for in-situ detection and feedback control. Feedback control and in-situ detection systems/methods provide current data and other pertinent information to the fabrication system rather than gathering this information at or near the end of the fabrication process. In addition, such in-line feedback methods/systems decrease yield loss, fabrication costs and produce less waste as fewer wafers are discarded and more wafers having closed area defects are processed further to reduce the defects. Furthermore, such methods facilitate mitigating recurrence of closed area defects on subsequent wafers.
Thus, an in-line system and method to detect and mitigate closed area defects in semiconductor wafers are desired to increase overall semiconductor quality and performance.
SUMMARY
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description presented later.
The present invention provides a system and a method for in-situ detection and reduction of closed area defects in wafers having a grating pattern etched thereon. The present invention facilitates controlling quality and mitigating yield loss in semiconductor fabrication by signaling to the fabrication system (and to a user) that a subject wafer contains closed area defects of a determined magnitude and thus requires additional processing to reduce the defects. In addition, the present invention involves regulating the fabrication process using run-time feedback, which facilitates detection and reduction of closed area defects on subsequently fabricated wafers. The run-time feedback or feedback control permits data related to detected closed area defects to be communicated back to fabrication components. In response to the data, the fabrication components make adjustments accordingly so as to mitigate subsequent occurrences of closed area defects on the grating patterns and on the wafer in general.
As a result, the present invention provides improved semiconductor fabrication as compared to conventional systems by facilitating the achievement of smaller feature sizes and higher packing densities while mitigating yield loss and the occurrence of closed area defects in subsequent wafers.
An exemplary system for in-situ detection and reduction of closed area defects on a wafer may employ one or more light sources arranged to project light onto a grating pattern developed on a wafer and one or more light detecting devices (e.g. photo detector, photodiode) for detecting light signatures reflected by the grating. The light signature reflected from the grating (and wafer) is characteristic of the presence (or absence) of losed area defects (e.g. intrusion defects, extrusion defects, corner defects, pinhole defects.
A processor receives the reflected light signature from the light detector and processes it by converting or interpreting the reflected light into an associated data form, such as numerical or graphical data, in order to determine the presence of closed area defects. The processor may also determine a quantity or level of defects present using the reflected light signature. Determining the presence and level of closed area defects is performed by comparing the data associated with the reflected light signature (subject grating pattern) with known light signatures in connection with known grating patterns.
In addition, the processor may compare the actual level of detected closed area defects to a threshold level of closed area defects to determine whether enough closed area defects are present to constitute “a positive detection”. Information produced and assimilated by the processor is then communicated to a controller for dete

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