Amplifiers – With semiconductor amplifying device – Including plural stages cascaded
Reexamination Certificate
2000-07-13
2003-12-30
Shingleton, Michael B (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including plural stages cascaded
C330S267000, C330S292000
Reexamination Certificate
active
06670851
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits and, in particular, to amplifier integrated circuits with frequency compensation capability.
2. Description of the Related Art
Amplifier integrated circuits (ICs) constitute one of the basic types of analog integrated circuits. Amplifier ICs are essentially configured to receive an input voltage signal (V
in
), or input current signal, and, in response, provide a larger output voltage signal (V
out
), or larger output current signal. Such amplifier ICs can be used, for example, as an audio power amplifier or to drive a cathode ray tube (CRT).
FIG. 1
is a simplified electrical schematic diagram of a conventional cascode amplifier IC
10
. Conventional cascode amplifier IC
10
includes an input bias terminal
12
, a power supply input terminal
14
, an input signal terminal
16
and an output signal terminal
18
. In conventional cascode amplifier IC
10
, bipolar transistor X
5
(configured as a PNP emitter-follower) functions as an input buffer stage circuit. Such an input buffer stage circuit minimizes the current loading of any pre-amplifier devices (e.g., a video pre-amplifier, not shown). Resistor R
9
is configured to turn on bipolar transistor X
5
when there is no input voltage signal (V
in
). Resistor R
6
functions as a pull-up resistor for bipolar transistor X
5
and also limits the current flow therethrough.
Bipolar transistors X
1
and X
2
are arranged in a cascode configuration to provide a gain stage circuit. For example, bipolar transistor X
1
can be a low voltage and very fast bipolar transistor, while bipolar transistor X
2
can be a higher voltage bipolar transistor than X
1
. The cascode configuration of bipolar transistors X
1
, X
2
, in this situation, provides the equivalent of a very fast and high voltage bipolar transistor. Resistors R
2
, R
3
set the current flow through bipolar transistors X
1
, X
2
, while the resistance ratio of resistors R
2
and R
3
sets the gain (i.e., amplification) of conventional high frequency cascode amplifier IC
10
. Resistor R
b
limits the current through bipolar transistor X
2
. Bipolar transistors X
3
, X
4
are configured to function as an output buffer stage circuit. Bipolar transistor X
6
, along with resistors R
7
, R
8
, are configured as a bias stage circuit and set the bias current through bipolar transistors X
3
, X
4
when there is no change in the level of the input voltage signal V
in
.
For a conventional cascode amplifier IC to successfully operate in the high frequency (i.e., high speed) regime, it should possess a frequency compensation capability that improves the high frequency response of the conventional cascode amplifier IC.
FIG. 2
is a schematic simulation diagram of conventional high frequency cascode amplifier IC
20
with frequency compensation capability. The conventional high frequency cascode amplifier IC
20
is configured to assert an amplified output voltage signal V
out
(at output signal terminal
22
) in response to input voltage signal V
in
(received at input signal terminal
24
), when biased by bias voltage V
b
(received at input bias terminal
26
) and provided with power supply voltage V
cc
(received at power supply input terminal
28
).
Conventional high frequency cascode amplifier IC
20
includes an input buffer stage circuit
30
that includes bipolar transistor X
87
, a gain stage circuit
32
that includes bipolar transistors X
91
, X
85
, an output buffer stage circuit
34
that includes bipolar transistors X
81
, X
82
, X
83
and X
89
, and a bias stage circuit
36
that includes bipolar transistor X
84
. Conventional high frequency cascode amplifier IC
20
also includes a resistance-capacitance (RC) series circuit
40
. RC series circuit
40
is configured to provide for frequency compensation (also referred to as frequency “peaking”) during operation of the conventional high frequency cascode amplifier IC
20
. The RC series circuit
40
includes resistors R
112
, R
102
that are electrically connected in series with two metal-polysilicon peaking capacitors C
63
, C
102
. As depicted in
FIG. 2
, RC series circuit
40
provides for frequency compensation by feeding the amplified output signal (V
out
) back to an emitter of bipolar transistor X
91
of the gain stage circuit
32
of the conventional high frequency cascode amplifier IC
20
through the RC series circuit
40
.
One skilled in the art will recognize that
FIGS. 1 and 2
are representative of a variety of well known conventional cascode amplifier IC configurations. Further descriptions of cascode amplifier ICs are included in U.S. Pat. No. 5,977,610 to Hon Kin Chiu, “Analysis and Design of Analog Integrated Circuits, Third Edition” by P. R. Gray and R. G. Meyer, pp. 225-226, 464-466 and 511-513 (John Wiley & Sons, 1993), and co-pending application Ser. No. 09/615,527, Hon Kin Chiu, “Cascode Amplifier Integrated Circuit With Reduced Miller Capacitance at an Output Buffer Stage During a Transient Fall Response”), each of which is hereby fully incorporated by reference.
A drawback of conventional cascode amplifier ICs with frequency compensation capability is a wide variation in transient rise and fall times. Such a wide variation is due to inherent tolerances in the speed of the bipolar transistors in the circuits, as well as in the capacitance of the metal-polysilicon peaking capacitors. These inherent tolerances are caused by variations in the manufacturing process. Consequently, a given conventional cascode amplifier IC may include either “fast” or “slow” bipolar transistors and metal-polysilicon peaking capacitors with either a minimum or a maximum capacitance.
There is, moreover, no relationship or tracking between the speed of the bipolar transistors and the capacitance of the metal-polysilicon peaking capacitors. If, for example, the bipolar transistors are “fast” and the metal-polysilicon peaking capacitors are at their typical value, the conventional cascode amplifier IC will tend to exhibit a transient overshoot. If, however, the bipolar transistors are “slow” and the metal-polysilicon peaking capacitors are at their minimum capacitance, the conventional cascode amplifier IC will exhibit long transient rise and fall times. The overall transient rise and fall time variation for conventional cascode amplifier ICs is, therefore, undesirably large.
FIGS. 3-6
depict the transient rise and fall responses for the conventional high frequency cascode amplifier IC of FIG.
2
.
FIG. 3
depicts the transient rise response for the circumstances of “fast” transistors (curve
3
A) and “slow” transistors (curve
3
B) and metal-polysilicon peaking capacitors with typical capacitance values. For the fast transistors, the transient rise time is approximately 3.40 nano-seconds, while for the slow transistors it is approximately 3.86 nano-seconds.
FIG. 4
depicts the transient fall response for the circumstances of “fast” transistors (curve
4
A) and “slow” transistors (curve
4
B) and metal-polysilicon peaking capacitors with typical capacitance values. For the fast transistors, the transient fall time is approximately 3.69 nano-seconds, while for the slow transistors it is approximately 4.23 nano-seconds.
FIG. 5
depicts the transient rise response for the circumstances of “fast” transistors with metal-polysilicon peaking capacitors at their maximum value (curve
5
A) and “slow” transistors with metal-polysilicon peaking capacitors at their minimum capacitance value (curve
5
B). For curve
5
A, the transient rise time is approximately 3.29 nano-seconds, while for curve
5
B it is approximately 4.03 nano-seconds.
FIG. 6
depicts the transient fall response for the circumstances of “fast” transistors with metal-polysilicon peaking capacitors at their maximum value (curve
6
A) and “slow” transistors with metal-polysilicon peaking capacitors at their minimum capacitance value (curve
6
B). For curve
6
A, the transient fall time is approximately 3.53 nano-seconds, while for curve
6
B it is approximately 4.
Chiu Hon Kin
Hojabri Peyman
Girard & Equitz LLP
National Semiconductor Corporation
Shingleton Michael B
LandOfFree
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