Silicon carbide semiconductor device

Details Silicon carbide semiconductor device Silicon carbide semiconductor device

1999-03-10

2003-06-03

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Specified wide band gap semiconductor material other than...

Diamond or silicon carbide

C257S076000, C257S328000, C257S329000, C438S105000, C438S212000, C438S268000, C438S931000

Reexamination Certificate

active

06573534

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a silicon carbide semiconductor device such as, for example, an insulated gate type field effect transistor and especially a high power vertical MOSFET.
2. Description of the Related Art
A wide variety of vertical MOS transistor and other devices are conventionally known which employ SiC. Examples include those described in Japanese Unexamined Patent Publication No. 4-23977, U.S. Pat. No. 5,323,040, and Shenoy et al., IEEE Electron Device letters, vol. 18, No.3, pp.93-95, March 1997. The vertical MOS transistors disclosed in these documents are designed with high quality materials for high breakdown voltage and low ON resistance compared to MOS transistors formed from silicon.
It is an object of the present invention to provide a SiC MOS transistor which makes full use of the characteristics of SiC in order to obtain even lower ON resistance and higher breakdown voltage than conventional SiC MOS transistors, and which is designed for greater ease of use.
SUMMARY OF THE INVENTION
The present invention which achieves the object stated above is a semiconductor device comprising:
a semiconductor substrate comprising silicon carbide of a first conductivity type and a silicon carbide epitaxial layer of the first conductivity type which is formed on the main side of the semiconductor substrate,
a first semiconductor region formed on the main surface of the silicon carbide epitaxial layer and comprising silicon carbide of a second conductivity type,
a second semiconductor region formed on the first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the silicon carbide epitaxial layer of the first conductivity type by the first semiconductor region,
a third semiconductor layer formed on the first semiconductor region, connected to the silicon carbide epitaxial layer and the second semiconductor region, comprising silicon carbide of the first conductivity type, and of higher resistance than the silicon carbide epitaxial layer or semiconductor substrate, and a gate electrode formed on the third semiconductor region with an insulating layer there between,
wherein the third semiconductor layer is depleted when no voltage is being applied to the gate electrode so that said semiconductor device has normally OFF characteristic.
According to this construction, the third semiconductor layer (thin channel epi-layer) is depleted and exhibits a normally OFF characteristic when no voltage is applied to the gate electrode. At such times, the third semiconductor layer must have its depleted layer extending across the full width between the first semiconductor base region and the gate insulating film to exhibit a normally OFF characteristic, but it is not necessary for the depleted layer to extend completely across the entire length of the third semiconductor layer. In particular the depletion of the third semiconductor layer is not necessary where the third semiconductor layer extends to the second semiconductor source region or the region contacting the silicon carbide epitaxial layer of first conductivity type (drift region).
In the construction described above, when a voltage is applied to the gate electrode to form an electric field on the gate insulating layer, an accumulation-type channel is induced on the third semiconductor layer (thin channel epi-layer), and the carrier flows between the source electrode and drain electrode (i.e., an ON state is achieved).
This design can address the low channel mobility problem of conventional inversion mode SiC power transistor, since the device operates in an accumulation mode. It was demonstrated in Si electronic devices that, the accumulation layer channel mobility is much higher than the inversion layer channel mobility (See for example, S. C. Sun et al., IEEE. Trans. Electron Device, Vol.ED-27, pp.1497, 1980). The same can be applied to MOS based SiC power devices. A large reduction in the ON resistance can also be expected for accumulation mode SiC power devices.
The normally OFF characteristic of the third semiconductor layer is achieved by mutually connecting the depleted layer which extends between the gate electrode and the third semiconductor layer, and the depleted layer between the second semiconductor layer and the third semiconductor layer. Thus, according to the silicon carbide semiconductor device of the present invention, the impurity concentration and thickness of the third semiconductor layer, and the second semiconductor region and gate electrode allow total depletion of the third semiconductor layer even when no voltage is being applied to the gate electrode, thus allowing a normally OFF characteristic to be achieved so that it can be used like a conventional normally OFF device.
Furthermore, according to the semiconductor device of the invention, the impurity concentration of the first semiconductor base region and the impurity concentration of the third semiconductor layer in which the channel is formed are independently controlled, to give a silicon carbide semiconductor device with high breakdown voltage, low current loss and a low threshold voltage. That is, the impurity concentration of the first semiconductor region may be increased, so that while maintaining a high breakdown voltage between the source and drain, the depth of the first semiconductor base region can be shorten to reduce the junction field effect (JFET-effect). In addition, since the impurity concentration of the channel may be decreased to reduce the effect of impurity scattering during flow of the carrier, the channel mobility may be thereby increased. As a result it is possible to obtain a silicon carbide semiconductor device with high breakdown voltage and low current losses.
The silicon carbide semiconductor device of the present invention is a planar vertical field effect transistor, but it may also be applied to planar or trench-type transistors.
A planar-type semiconductor device according to the invention comprises the following:
a semiconductor substrate of a first conductivity type comprising single crystal silicon carbide and a silicon carbide epitaxial layer of the first conductivity type which is formed on the main side of the semiconductor substrate and has a lower dopant concentration than the semiconductor substrate,
a first semiconductor base region of a second conductivity type formed on a predetermined region of the silicon carbide epitaxial layer to a predetermined depth,
a second semiconductor source region of the first conductivity type formed on a predetermined region of the base region and having a shallower depth than the base region,
a third semiconductor surface channel layer of the first conductivity-type made of silicon carbide, and situated so as to connect the source region and the silicon carbide epitaxial layer of the first conductivity type and the second semiconductor base region,
a gate insulating layer formed on the surface of the surface channel layer, a gate electrode formed on the surface of the channel layer,
a source electrode formed in contact with the base region and source region, and
a drain electrode formed on the back side of the semiconductor substrate.
The following are preferred embodiments of the planar-type semiconductor device.
(1) The main surface of the silicon carbide semiconductor substrate is (0001) Si face, (000{overscore (1)}) C-face, (11{overscore (2)}0) a-face or (1{overscore (1)}00) prism-face. The (0001) Si face or (11{overscore (2)}0) a-face is preferred for the low interface surface state of the silicon carbide/insulator interface.
(2) The dopant concentration of the surface channel layer is no greater than the dopant concentrations of the silicon carbide epitaxial layer and the base region.
(3) The gate electrode has a first work function potential, the base region has a second work function potential, the surface channel layer has a third workfunction potential, and the first, second and third workfunction potentials are set so that the carrier of the first con

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