Signal processing apparatus which performs logarithmic...

Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit

Reexamination Certificate

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C250S201200

Reexamination Certificate

active

06642500

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a photoelectric conversion apparatus having a logarithmic compression function.
2. Related Background Art
A conventional photoelectric conversion apparatus for modulating electronic flash light from a camera has used a circuit as shown in FIG.
1
. In
FIG. 1
, a photodiode
1
for receiving electronic flash light is connected to an operational amplifier
2
. An npn bipolar transistor
10
logarithmically compresses a photocurrent I
P
. An npn bipolar transistor
11
applies a gain to a logarithmically compressed signal to expand it. An integral capacitor
7
integrates an expansion current I. This photoelectric conversion apparatus further comprises a comparator
8
and monitoring voltage follower
9
.
Letting I
P
be the photocurrent of the photodiode
1
, an output V
1
from the logarithmic compression circuit is given by
V
1
=
V
c
-
kT
q

ln

I
p
I
s
(
1
)
where k is the Boltzmann constant, T is the temperature, q is the elementary charge, and I
S
is the reverse saturation current of a bipolar transistor Q
1
.
The output of the logarithmic compression circuit is connected to the emitter of an expansion transistor Q
2
. Letting V
DAC
be the base potential of the expansion transistor, the current I flowing through the expansion transistor Q
2
is given by
I
=
I
S

exp

q

(
V
DAC
-
V
1
)
kT
=
I
P

exp

q
kT

(
V
DAC
-
V
C
)
(
2
)
The expansion current I gains by the potential difference between V
DAC
and V
C
. For example, for V
DAC
−V
C
=18 mV, the expansion current is double the photocurrent I
P
.
However, the prior art adopts bipolar transistors as elements for logarithmically compressing, expanding, and integrating a current, so the following problems occur.
a. The bipolar technique is necessary, and is less compatible with a CMOS sensor (sensor manufactured by a CMOS process).
b. The cost is high in terms of the number of masks and the process.
SUMMARY OF THE INVENTION
It is the first object of the present invention to provide an apparatus which can be manufactured by a CMOS process.
It is the second object of the present invention to provide a multifunctional CMOS sensor capable of reducing the cost by integrating a modulated light circuit in another CMOS sensor, e.g., an autofocus sensor on a single chip.
To achieve the above objects, according to an aspect of the present invention, there is provided a signal processing apparatus comprising:
a photoelectric conversion element;
a compression device which logarithmically compresses an output from the photoelectric conversion element;
an expansion device which exponentially expands an output from the compression device; and
an integral device which integrates an output from the expansion device,
wherein a transistor which integrates logarithmic compression in the compression device and a transistor which performs exponential expansion in the expansion device are MOS transistors respectively.
According to another aspect of the present invention, there is provided a signal processing apparatus comprising:
a photoelectric conversion element;
a compression device which logarithmically compresses an output from the photoelectric conversion element; and
an integral device which integrates an output from the expansion device,
wherein a transistor which performs logarithmic compression in the compression device and a transistor which performs exponential expansion in the expansion device are MOS transistors respectively.
According to still another aspect of the present invention, there is provided a signal processing apparatus formed by a CMOS process on a single semiconductor substrate, comprising:
a modulated light circuit including:
a compression device which logarithmically compresses an output from a photoelectric conversion element;
an expansion device which exponentially expands an output from the compression device; and
an integral device which integrates an output from the expansion device,
wherein a transistor which performs logarithmic compression in the compression device and a transistor which performs exponential expansion in the expansion device are MOS transistors respectively; and
a focus adjustment circuit.
The above and other objects and features of the present invention will be apparent from the following description in conjunction with the accompanying drawings.


REFERENCES:
patent: 3600589 (1971-08-01), Hanson
patent: 3679905 (1972-07-01), Watanabe
patent: 3843880 (1974-10-01), Tsuchiyasu
patent: 4633077 (1986-12-01), Ikari et al.
patent: 4758797 (1988-07-01), Wermuth
patent: 4808811 (1989-02-01), Kumakura et al.
patent: 5260738 (1993-11-01), Yamagishi et al.
patent: 5990718 (1999-11-01), Tchamov et al.
patent: 6043525 (2000-03-01), Chen
patent: 6262623 (2001-07-01), Molnar

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