Transmission-gate based flip-flop

Details Transmission-gate based flip-flop Transmission-gate based flip-flop

2001-12-06

2003-11-04

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S202000, C327S206000

Reexamination Certificate

active

06642765

ABSTRACT:

BACKGROUND
This invention relates to flip-flops.
Flip-flops are used in VLSI systems to keep signals correlated in time. Modern microprocessors use a large array of flip-flops that are chosen to suit speed and output load requirements. Most microprocessor signal paths are non-critical, and surplus timing use for energy reduction is possible for logic blocks and flip-flops in these paths. As the number of logic gates which lie between signal path flip-flops decrease, the relative impact of the timing delay and energy consumption in the logic gates is reduced, and the relative impact of the timing delay and energy consumption of the flip-flops increases as does the benefit of using low-energy flip-flop designs.
One type of low-energy flip-flop is the master-slave latch pair. As shown in
FIG. 1
, one such low-energy master-slave latch pair flip-flop is a transmission-gate based flip-flop (TGFF)
10
where n-MOS-only clocked transistors
20
,
30
are used to reduce energy consumption. However, on-path inverters
40
,
50
, which are interrupted by clock signals “CP” and “CN”
60
,
70
, respectively, slow down the flip-flop and increase the energy consumed. Also, inverter
90
places a logic level 1 at {overscore (Q
M
)}
100
when input
80
is at logic level 0 and clock signal “CN”
70
is activated with a logic level 1. However feedback inverter
110
cannot invert the logic level 1 at {overscore (Q
M
)}
100
due to a logic level 0 at clock signal “CP”
60
that disables inverter
110
. Therefore inverter
90
is unnecessarily consuming energy by “pulling-up” the voltage level at {overscore (Q
M
)}
100
.
In another known flip-flop architecture
130
, shown in
FIG. 2
, pull-up transistors of inverters
90
,
120
of
FIG. 1
are removed, leaving NMOS transistors, to save energy. However, non-interrupted feedback inverters
140
,
150
cause excessive short-circuit energy consumption and a longer time delay arising from a contention with the transmission-gates
160
,
170
. Inverter
180
is not necessary because the input of the inverter
140
can be connected to {overscore (Q
M
)}
190
.


REFERENCES:
patent: 5250852 (1993-10-01), Ovens et al.
patent: 5854565 (1998-12-01), Jha et al.
patent: 6198324 (2001-03-01), Schober
patent: 6211713 (2001-04-01), Uhlmann
Suzuki, K. Odagawa, and T. Abe, Clocked CMOS Calculator Circuitry, IEEE Journal of Solid State Circuits, vol. DC-8, pp. 462-469, Dec. 1973.
G. Gerosa et al., “2.2W 80 MHz superscalar RISC Processor,” IEEE Journal of Solid-State Circuits, vol. 34, No. 12, pp. 247-254, Dec. 1994.
S. Hsu and S-L. Lu, A Novel High-Performance Low-Power CMOS Master-Slave Flip-Flop, In Proc. Twelfth Annual IEEE ASIC/SOC Conf. 1999, pp. 340-343.
H. Takahashi, “Low-Power and High Performance Circuit Design of General Purpose DSPs,” in Proc. VLSI Circuits Short Course 20001 (at VLSI Symp. 2001), p. 87.

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