Multiplex communications – Data flow congestion prevention or control – Control of data admission to the network
Reexamination Certificate
1998-06-17
2003-02-11
Hsu, Alpus H. (Department: 2665)
Multiplex communications
Data flow congestion prevention or control
Control of data admission to the network
C370S252000, C370S395100
Reexamination Certificate
active
06519226
ABSTRACT:
TECHNICAL FIELD
This invention relates to packet communications networks. More specifically, this invention relates to interface circuits used in packet communications networks.
BACKGROUND
Broadband integrated services digital networks (B-ISDN) are digital packet networks which may be based upon the asynchronous transfer mode (ATM) protocol being standardized by the CCITT. In ATM, data is transported at 155 Mb/sec, or multiples of 155 Mb/sec, in fixed size cells comprising 53 bytes. Each ATM cell comprises 48 bytes of data to which a 5 byte header is appended. The header of an ATM cell comprises a group of identifiers including a virtual path identifier (VPI) and a virtual channel identifier (VCI) which uniquely specify the call or connection (virtual circuit) to which the cell belongs. When an ATM cell arrives at an input to a switch in an ATM network, its header, containing a VPI and a VCI representing the virtual path and virtual channel to which the cell belongs on an input link to the switch, is examined to determine where the cell is to be routed. The header is also changed so that it contains a new VPI and VCI indicating the virtual path and the virtual channel to which the cell will belong on an output link from the switch.
Existing integrated circuit chips which do this processing are usually called header translation units and perform the following two operations, header modification and manipulation of local routing tags. Header translation units modify one or both of the virtual path identifier and the virtual channel identifier (VPI/VCI) in the ATM header. Prior header translation units typically do a table look up to accomplish this. Specifically, those units include a random access memory containing a new header to be attached to each ATM cell. A predetermined portion of the old header of an ATM cell is used to address the random access memory at the location of the new header for the ATM cell. In addition to providing a new header for each ATM cell; header translation units also may attach a routing tag to each ATM cell to cause an ATM switch to route the cell to an appropriate switch output and output link. The first operation is required by B-ISDN standards to route ATM cells through different virtual paths on different links. The second operation is internal to ATM switches and depends on the type of switch used. These two operations are the minimum operations required for transporting ATM cells through a network. Other operations, however, would be useful in ATM interfaces. Those other operations include inserting cells into and extracting cells from ATM links between ATM switches, policing bandwidth usage of communications channels between ATM switches and communications channels between users and the network, and gathering statistics to evaluate network performance. In the past, these functions, if they were performed at all, had to be performed by separate chips in addition to the header translation unit. Multiple table look ups in random access memories in addition to the table look up in the random access memory of the header translation unit are required. This multiplicity of chips and table look ups results in space consuming and complex circuitry and long time delays in accomplishing the functions described above. In addition, prior circuitry was inflexible in that not all of the ATM header could be used to perform table look up operations. That prior circuitry also did not have convenient facilities for selectively removing ATM cells from a cell stream flowing through an ATM switch or for selectively adding ATM cells to that cell stream. Prior circuitry thus did not lend itself naturally to distributed switch control. It required a central controller which limited cell processing speed.
SUMMARY
The problems described above are solved, in an example of the invention, by an asynchronous transfer mode interface (ATM layer interface) which comprises a content addressable memory responsive to a selectable and predetermined part of an ATM cell received by the interface. The content addressable memory produces an address signal directed to a random access memory which produces at least one parameter block relating to the ATM cell. In one example of the invention, the parameter block comprises a new ATM header for the cell. In another example of the invention, the parameter block comprises a local header to be appended to the ATM cell. In yet another example of the invention, the parameter block may comprise a network usage parameter which can be used to police traffic flow through an ATM network. Typical usage parameters may include a bandwidth usage parameter or a burstiness parameter. Suitable action may be taken to detect and police violations of these parameters by the communications traffic in the network. For example, a leaky bucket algorithm may be implemented to detect network usage violations. In some examples of the invention, an ATM interface circuit may be provided with a local input/output interface which permits selective addition of ATM cells to an ATM cell stream flowing between a main input and a main output of the ATM interface circuit. That local input/output interface also permits selective extraction of ATM cells out of that ATM cell stream. A selective amount of ATM cell processing may thus be performed in hardware in ATM interface integrated circuit chips and a selective amount of ATM cell processing may be performed in software in local control processors. Functions such as header translations, error checking, and policing could be performed in hardware for the most heavily used virtual circuits and in software by the local control processor for the rest of the VCs. This permits an ATM network to use the entire virtual path and virtual circuit space (
2
28
virtual circuits corresponding to the 28 bits in the VCI/VPI field in an ATM header), even though the ATM interface may not have the capacity to hold and process information pertaining to all of the virtual circuits. In addition, signaling and bandwidth management and routing functions would be performed by the local control processor. Distributed control of ATM switches thus is conveniently achieved.
This is only a summary of certain aspects of the invention disclosed in this application. The full scope of the exclusionary right is defined in the claims at the end of the application.
REFERENCES:
patent: 4630266 (1986-12-01), Deparis et al.
patent: 5121383 (1992-06-01), Golestani
patent: 5142653 (1992-08-01), Schefts
patent: 5343463 (1994-08-01), Van Tetering et al.
patent: 5390188 (1995-02-01), Dawson
patent: 5457700 (1995-10-01), Merchant
patent: 5790524 (1998-08-01), Bennett et al.
patent: 5793976 (1998-08-01), Chen et al.
patent: 5850385 (1998-12-01), Esaki
Kumar Vijay P.
Lin Horng-Dar
O'Neill Jay Henry
Oechslin Philippe
Ouellette, III Edward Joseph
Hsu Alpus H.
Lucent Technologies - Inc.
Opalach Joseph J.
Troutman Sanders Mays & Valentine
LandOfFree
Packet network interface does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Packet network interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Packet network interface will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3154837