Static information storage and retrieval – Floating gate
Reexamination Certificate
2001-07-30
2003-02-25
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
C365S185050, C365S185330
Reexamination Certificate
active
06525959
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to high performance microelectronic flash memory cells and to the art of manufacturing high performance microelectronic flash memory cells. Even more specifically, this invention relates to high performance microelectronic flash memory cells with reduced common source resistance and to the art of manufacturing high performance microelectronic flash memory cells with reduced common source resistance.
2. Discussion of the Related Art
A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory array are made small by omitting transistors known as select transistors that enable the cells to be erased independently. As a result, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, a drain, a floating gate and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, or to erase all of the cells as a block.
The cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells in a either a column or a row are connected together and each column or row common source connections are then connected to a common source voltage V
SS
. This arrangement is known as a NOR flash memory configuration.
A cell is programmed by applying a voltage, typically 9 volts to the control gate, applying a voltage of approximately 5 volts to the drain and grounding the common voltage source V
SS
, which causes hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative change therein which increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell is read by applying typically 5 volts to the control gate, applying 1 volt to the bitline to which the drain is connected, grounding the common source voltage V
SS
, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, a cell is erased by applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. A cell can also be erased by applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float. Another method of erasing is by applying 5 V to the P-well and minus 10 V to the control gate while allowing the source/drain to float.
As discussed above, the cells are arranged in rows and columns with the sources connected to a common line either in a row or a column. Because there is finite resistance in the source lines, the number of cells between each source line contact is limited.
Therefore, what is needed is a memory array and a method to manufacture the memory array that reduces the source line resistance in high density flash arrays without increasing the short channel effects.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are obtained with a flash memory array that includes conductive lines connecting the source lines.
In accordance with one aspect of the invention, a flash memory array composed of multiple memory cells organized in rows and columns with source lines connecting the sources of memory cells in a row and buried conductive lines transverse to the source lines connecting the source lines with the source lines connected to a source voltage line parallel to the bitlines.
In accordance with another aspect of the invention, the buried conductive lines are formed at the bottom of trenches formed in a semiconductor substrate in which the flash memory is to be formed.
In accordance with another aspect of the invention, a flash memory array composed of multiple memory cells organized in rows and columns with source lines connecting the sources of memory cells in a row and buried conductive lines transverse to the source lines connecting the source lines with the buried conductive lines connected to a source voltage line parallel to the wordlines
The described invention thus provides a flash memory array with reduced V
SS
resistance without degrading the short channel behavior of the core cell.
REFERENCES:
patent: 5646888 (1997-07-01), Mori
patent: 6031765 (2000-02-01), Lee et al.
patent: 6239465 (2001-05-01), Nakagawa
patent: 6274907 (2001-08-01), Nakagawa
Advanced Micro Devices , Inc.
Auduong Gene N.
Hoang Huan
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